ECE 448

FPGA and ASIC Design with VHDL

Spring 2009

Instructor

Kris Gaj
S&T 2, room 223
e-mail: kgaj (at) gmu.edu
Please start a subject of your e-mail from "ECE 448:"

Teaching Assistants

Tuesday section
Tuesday, 7:20-10:00 PM

Ekawat "Ice" Homsirikamol
Mailbox: S&T 2 hallway near Room 208
e-mail: ehomsiri (at) gmu.edu
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e-mail from "ECE 448:"

Wednesday & Thursday sections
Wednesday, 7:20-10:00 PM
Thursday, 7:20-10:00 PM

Marcin Rogawski
Mailbox: S&T 2 hallway near Room 208
e-mail: mrogawsk (at) gmu.edu
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e-mail from "ECE 448:"

Lecture:

Tuesday, Thursday, 3:00-4:15 PM, Krug Hall 253

Labs:

Section 201: Tuesday, 7:20-10:00 PM, S&T 2, Room 203
Section 203: Wednesday, 7:20-10:00 PM, S&T 2, Room 203
Section 202: Thursday, 7:20-10:00 PM, S&T 2, Room 203

All students will be provided with an access code to the room 203, and are welcome to work on their experiments at any time.
Experiment demonstrations will be accepted exclusively during the class time for a particular lab section.

Tentative list of office hours:

Monday, 5:30-7:00 PM, Ekawat "Ice" Homsirikamol
Tuesday, 1:00-2:30 PM, Marcin Rogawski
Tuesday, 4:30-5:30 PM, Kris Gaj
Wednesday, 1:00-2:30 PM, Marcin Rogawski
Thursday, 4:30-5:30 PM, Kris Gaj

All office hour sessions are open to all students, independently of their assignment to a particular lab section.

Course credit:

4 hours

Grading

Lab experiments & homework (Part I): 20%

Midterm exam for the lecture: 10%

Midterm exam for the lab: 15%

Quizzes 10%

Lab experiments & homework (Part II): 20%

Final exam: 25%

General Laboratory Rules

Each lab experiment will be preceded by an introduction and a hands-on session taught by a TA.

he deadlines for submitting all experiment deliverables (including source codes, diagrams, waveforms, configuration files, etc.) are being set as follows:

Tuesday section - Tuesday, 7:00 PM
Wednesday section - Wednesday, 7:00 PM
Thursday section - Thursday, 7:00 PM.

Students will be required to demonstrate working experiment during a lab session on a day designated as a due date for a particular lab experiment.

Experiment demonstrations will be accepted exclusively during the class time for a particular lab section.

For each experiment, the demonstration and the electronic deliverables (including lab report) are each worth 50% of points allocated to a given experiment.

Each lab experiment that is late will be penalized by deducting 1/3 of its allocated points per number of weeks that is late. As a result, no credit will be received for a lab experiment that is more than two weeks late. The additional opportunities will be provided to earn bonus points by completing additional requirements for each experiment or by completing experiment a week or more ahead of schedule. Both penalty and bonus points will apply independently to the demonstrations and to the electronic deliverables.

Office hours will be devoted to helping students with their experiments and answering any questions related to the subject of the course.

Students are required to work individually on all experiments from Part I of the course, and either individually or in groups of two students on all experiments from Part II of the course. In case of the group work, both students are expected to be intimately familiar with the entire solution to the given experiment and the entire experiment report. This knowledge will be verified during the experiment demonstration and the same grade will be applied to the entire team.

Every completed experiment must be presented to your TA, who will evaluate students results and effort. It is the students' responsibility to convince the TA that their designs work as required. Therefore, students have to simulate and test their designs thoroughly and well document their work. The TA is not required to test anything by himself nor to investigate if the designs are correct in case of insufficient documentation.

In order to prevent cheating and plagiarism, the students will be required to
- submit all electronic deliverables using Blackboard at the designated time before the experiment demonstration,
- restrain from any changes in the experiment files in the period between the electronic submission and the experiment demonstration,
- answer correctly several detailed questions regarding their experiment solution at the time of demonstration.
Not complying with either of these requirements may lead to either a total rejection of the demonstration by the TA, or to a substantial reduction of the number of points awarded to the student.

In case of any evident attempt to submit somebody's else work as your own, both students involved in the incident may be penalized by taking away all points for the given experiment. The two repeated attempts to present somebody's else work as your own may lead to the F grade for the entire course, independently of the total amount of points earned by the student before the second incident.

The students are encouraged to help and support each other in all problems related to the
- operation of the CAD tools,
- operation of the FPGA boards,
- operation of the measurement equipment available in the lab,
- understanding of the problem to be solved during each experiment.

Lecture slides & VHDL codes (to be published before each lecture)

Posted gradually typically one day before a given lecture.

NEW!!! - Lecture 21 - FPGA Platforms. High-Level Language Design Flows. - NEW!!!

Lecture 20 - ASIC Front-End Design

Lecture 19 - PicoBlaze Interrupt Interface and Assembly Code Development

Lecture 18 - PicoBlaze I/O Interface

Lecture 17 - PicoBlaze Overview

Lecture 16 - Features of Modern FPGAs

Lecture 15 - External SRAM

Lecture 14 - Xilinx FPGA Memories

Lecture 13 - Multipliers. Timing parameters.

Lecture 12 - VHDL Coding for Synthesis.

Lecture 11 - Advanced Testbenches.

Lecture 10 - RTL Design Methodology. Sorting example.

Lecture 9 - Modeling of Circuits with a Regular Structure. Aliases, Constants, Packages. Mixing Design Styles.

Lecture 8 - RTL Design Methodology. MIN_MAX_AVR example.

Lecture 7 - Finite State Machines

Lecture 6 - FPGA Devices & FPGA Design Flow

Lecture 5 - Sequntial-Circuit Building Blocks

Lecture 4 - Simple Testbenches. Behavioral Modeling of Combinational Logic.

Lecture 3 - Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic.

Lecture 2 - VHDL Refresher

Lecture 1 - Introduction and Organizational Issues

See Course Webpage from Spring 2008 for slides from the previous year.

Homework assignments

Posted gradually at least a week before a given assignment is due.

NEW!!! - Bonus Problem 1 - due Sunday, March 1, midnight - NEW!!!

See Course Webpage from Spring 2008 for homework assignments from the previous year.

List of experiments

The specifications of lab experiments will be posted gradually at least one day before a given experiment is introduced.

NEW!!! - Experiment 7 - Replacing Hardwired Control Unit with the Picoblaze Microcontroller - NEW!!!

Experiment 6 - Internal FPGA Memories, Pseudorandom Number Generator, Advanced Testbenches

Experiment 5 - Displaying patterns on the VGA monitor

Experiment 4 - Vending Machine - designing digital systems using block diagrams and finite state machines

Experiment 3 - implementing digital systems using FPGAs (functional, post-synthesis & timing simulation, experimental verification with the board)

Experiment 2 - implementing sequential logic in VHDL - Key Debouncing; PicoBlaze 8-bit Embedded Microcontroller

Experiment 1 - implementing combinational logic in VHDL - Arithmetic Logic Unit and Instruction Decoder of the PicoBlaze 8-bit Embedded Microcontroller

See Course Webpage from Spring 2008 for specifications of experiments from the previous year.

Lab slides & VHDL codes (to be published before each lab session)

Posted gradually at least one day before a given experiment is introduced.

NEW!!! - Lab 7 - Replacing Hardwired Control Unit with the Picoblaze Microcontroller. Programming of Picoblaze. - NEW!!!

Lab 6 - Internal FPGA Memories, Pseudorandom Number Generator, Advanced Testbenches

Lab 5 - VGA Signal Generator

Practice Lab Exam

Lab 4 - Finite State Machines. FPGA Design Flow based on Xilinx ISE.

Lab 3 - FPGA Design Flow based on Aldec Active-HDL. FPGA Boards.

Lab 2 - Introduction to ModelSim HDL Simulator. Implementing Sequential Logic in VHDL.

Lab 1 - Review of Aldec Active HDL. Implementing Combinational Logic in VHDL: MLU and miniALU.

See Course Webpage from Spring 2008 for slides from the previous year.

Software

The Detailed Instructions on How to Configure your FPGA Tools at School, and Install and Configure your FPGA Tools at Home

Tutorial on FPGA Design Flow based on Aldec Active-HDL

Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim

Tutorial on Concurrent Version System based on CVS NT and Tortoise CVS

NEW!!! - Tutorial on Hardware and Software Design Flow Based on PicoBlaze Microcontroller with Celoxica RC10 development board - NEW!!!

The FPGA design process will be based on the following design tools:

- Design Entry and Simulation: Active HDL from Aldec or ModelSim Xilinx Edition from Xilinx,
- Logic Synthesis: Synplify Pro from Synplicity or Xilinx XST from Xilinx,
- Implementation: Xilinx ISE or Xilinx WebPACK from Xilinx.

The ASIC design process (front-end) will be based on the following design tools:

- Logic Synthesis: Design Compiler from Synopsys
- Timing Analysis: PrimeTime from Synopsys.

Hardware

Celoxica RC 10 FPGA Boards

NEW!!! - Spartan 3 FPGA Family - NEW!!!

Digital oscilloscopes, Tektronics TDS 224, 100 MHz bandwidth, 1GS/s sample rate, 4 channels

Logic analyzer

Students are not required to purchase any boards or other equipment by themselves. The boards will be provided to the students during the lab sessions, office hours, and on-demand by checking out the boards from the research lab located in S&T 2, room 220, and Dr. Gaj's office, S&T 2, room 223.

Required textbooks

Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience, 2008, ISBN: 978-0-470-18531-5.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill © 2nd edition, 2005, ISBN: 0-07-249938-9.

Useful references

VHDL

VHDL Instructions: Templates & Examples

OpenCores Coding Guidelines

Web Page on Type-Casting in VHDL

The Low Carb VHDL Tutorial - by Bryan Mealy

FPGAs & FPGA Boards

Introduction to FPGA devices and tools

Documentation for Xilinx devices, and in particular for the Spartan 3 family

Celoxica RC10 FPGA Board User Manual

Aldec Active-HDL

Aldec Active-HDL - Getting Started

Xilinx ISE

Xilinx manuals for ISE software.

Synopsys

Introduction to Synopsys

Remote Access to Synopsys

Related course web pages

ECE 448:    Spring 2008    Spring 2007    Spring 2006

ECE 449:    Spring 2005    Spring 2004    Spring 2003

ECE 545:     Fall 2008 (with Dr. Hwang)    Fall 2006 (with Dr. Gaj)

Exams & Quizzes from Previous Years

NEW!!! - In-Class Midterm Exam from Spring 2008 - NEW!!!

In-Class Midterm Exam from Spring 2007

NEW!!! - Lab Midterm Exam from Spring 2008 - Tuesday Section - NEW!!!

NEW!!! - Lab Midterm Exam from Spring 2008 - Wednesday Section - NEW!!!

NEW!!! - Lab Midterm Exam from Spring 2008 - Thursday Section - NEW!!!

Hands-on Midterm Exam from Spring 2004:

Solutions to the Midterm Exam - Tuesday section

Solutions to the Midterm Exam - Thursday section

Hands-on Midterm Exam from Spring 2005:

Solutions to the Midterm Exam - Monday section

Solutions to the Midterm Exam - Tuesday section

Solutions to the Midterm Exam - Thursday section

Practice Midterm Exam from Spring 2006

Practice Hands-on Midterm Exam

Practice Final Exam from Spring 2006

Practice final exam - Parts I & II

Solutions to Practice final exam - Part I

Solution to Part 2 Problem 3 - 2to1mux.vhd, 16to1mux.vhd

Quizzes from Spring 2006

Quiz 1

Quiz 2 with solutions

Quiz 3

Quiz 4 with solutions

Quiz 5 with solutions

Final Exam from Spring 2006

Final Exam Part I - version 1

Final Exam Part II - version 1

Final Exam Part I - version 2

Final Exam Part II - version 2

Final Exam from Spring 2007

Final Exam Part I - version 1

Final Exam Part II - version 1

Final Exam Part I - version 2

Final Exam Part II - version 2

Maintainer of the page: Kris Gaj