Bonus Problem 1
 10 bonus quiz points
due Sunday, March 1, midnight


Write VHDL code corresponding to the block diagram and the ASM chart developed as a solution to the MIN_MAX_AVR problem solved in class on Thursday, February 19.

Write a testbench capable of verifying the operation of your code.

Synthesize and implement your code for n=16, and verify it through functional, post-synthesis, and timing simulation. Perform timing analysis, and determine the critical path of your circuit.

Your code should pass timing simulation when tested using instructor's testbench.

You can use the following code for RAM.

Submit your solutions using Blackboard, under ECE 448, section 001 (lecture).

Include at least the following deliverables:

  1. All source files used for synthesis and implementation of your circuit.
  2. Testbench.
  3. RTL view.
  4. Simulation waveforms from the functional, post-synthesis, and timing simulations, proving the correct operation of your circuit, and demonstrating the delay of its critical path.
  5. Report file from the static timing analysis.
  6. Your own report containing at least the following additional information:
    • Resource utilization.
    • Minimum clock period and maximum clock frequency after synthesis and after implementation.
    • Critical path.