ECE 448

FPGA and ASIC Design with VHDL

Spring 2010

Quick Links

Instructor

Kris Gaj
The Nguyen Engineering Building, room 3225
e-mail:  kgaj (at) gmu.edu
             Please start a subject of your e-mail from "ECE 448:"
 

Teaching Assistants

Monday section

Jeremy Kelly
e-mail: jeremy.a.kelly (at) gmail.com

Tuesday section

Jeremy Kelly
e-mail: jeremy.a.kelly (at) gmail.com


Wednesday section

John Pham
e-mail:  jhnphm (at) gmail.com


Thursday section

Brian Loop
e-mail: bdloop (at) gmail.com

Lecture:

Monday, Wednesday, 5:55-7:10PM, Lecture Hall 2

Labs:

Section 201: Tuesday, 7:20-10:00 PM, The Nguyen Engineering Building, Room 3208
Section 203: Wednesday, 7:20-10:00 PM, 
The Nguyen Engineering Building, Room 3208
Section 202: Thursday, 7:20-10:00 PM, The Nguyen Engineering Building, Room 3208
Section 204: Monday, 7:20-10:00 PM, The Nguyen Engineering Building, Room 3208

All students will be provided with an access code to the room 3208, and are welcome to work on their experiments at any time.
Experiment demonstrations will be accepted exclusively during the class time for a particular lab section.

Tentative list of office hours:

Saturday, 12:00-1:00 PM, John Pham, Engineering 3208
Monday,     7:30-8:30 PM, Kris Gaj,
Engineering 3225
Monday,    10:00-11:00 PM, Jeremy Kelly, Engineering 3208
Tuesday,    6:00-7:10 PM, Jeremy Kelly, Engineering 3208
Wednesday,  4:30-5:30 PM, Kris Gaj,
Engineering 3225
Wednesday, 7:30-8:30 PM, Brian Loop, Engineering 3204

All office hour sessions are open to all students, independently of their assignment to a particular lab section.

Course credit:

4 hours

Grading

Lab experiments (Part I):   20%
Midterm exam for the lecture:  10%
Midterm exam for the lab:  15%
Quizzes & homework  10%
Lab experiments (Part II):    20%
Final exam:  25%

General Laboratory Rules

Lecture slides & VHDL codes (to be published before each lecture)

Lecture 14 - ASIC Design

Measuring the Gap Between FPGAs and ASICs

Lecture 13 - PicoBlaze I/O and Interrupt Interface. Example of Assembly Language Routine.

Lecture 12 - PicoBlaze Overview

Lecture 11 - Survey of Reconfigurable Logic Technologies

Lecture 10 - Advanced Testbenches

Lecture 9 - RTL Design Methodology

Lecture 8 - Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code.

Lecture 7 - FPGA Devices & FPGA Design Flow.

Lecture 6 - Modeling of Circuits with a Regular. Aliases, Constants, Packages. Mixing Design Styles.

Lecture 5 - Sequential-Circuit Building Blocks.

Lecture 4 - Simple Testbenches. Behavioral Modeling of Combinational Logic.  - revised 02/07/2010 (slide 51)

Lecture 3 - Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic. - revised 02/02/2010 (slide 44)

Lecture 2 - VHDL Refresher

Lecture 1 - Introduction and Organizational Issues

Posted gradually typically one day before a given lecture.

See Course Webpage from Spring 2009 for slides from the previous year.
 

Homework assignments

         Posted gradually at least a week before a given assignment is due.

       See Course Webpage from Spring 2009 for homework assignments from the previous year.
 

List of experiments

NEW!!! - Experiment 7 - Sorting Using PicoBlaze. - NEW!!!

Experiment 6 - VGA Display. Mini-Chess Game.

Experiment 5 - serial communications and clock management: HDLC transmitter & receiver  - revised 03/18/2010, 8pm

Experiment 4 - implementing DSP circuits: FIR Filter

Experiment 3 - implementing pipelined arithmetic circuits in VHDL: Pipelined Array Multiplier

Experiment 2 - implementing sequential logic in VHDL: Stream Cipher Trivium - revised 02/07/2010 (interface & control unit diagram)

Experiment 1 - implementing combinational logic in VHDL - Arithmetic Logic Unit and Instruction Decoder of MIPS

The specifications of lab experiments will be posted gradually at least one day before a given experiment is introduced.

See Course Webpage from Spring 2009 for specifications of experiments from the previous year.

 

Lab slides & VHDL codes (to be published before each lab session)   

NEW!!! - Lab 7: Sorting Using PicoBlaze. Hardware/Software Co-Design Using PicoBlaze. - NEW!!!

Lab 6: VGA Display. Mini-Chess Game.

Lab 5: Serial Communications. Working with the Digilent Basys2 FPGA Board. - revised 03/18/2010, 8pm

Lab 4: FIR Filter. FPGA Design Flow Based on Xilinx ISE/WebPack & ModelSim.

Lab 3: Pipelined Array Multiplier. FPGA Design Flow Based on Aldec Active HDL.

Lab 2: Implementing Sequential Logic in VHDL: Stream Cipher Trivium. Simulation using ModelSim. 

Lab 1: Implementing Combinational Logic in VHDL: ALU of MIPS. Simulation in the Aldec Active HDL Environment.

Posted gradually at least one day before a given experiment is introduced.

See Course Webpage from Spring 2009 for slides from the previous year.

Software

The Detailed Instructions on How to Configure your FPGA Tools at School, and Install and Configure your FPGA Tools at Home

Introduction to Simulation with Aldec Active-HDL: Tutorial 1

Introduction to Simulation with Aldec Active-HDL: Tutorial 2

Tutorial on FPGA Design Flow based on Aldec Active-HDL (revised Feb 20, 2010)

Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim (revised, Feb 21, 2010)

Tutorial on Concurrent Version System based on CVS NT and Tortoise CVS

The FPGA design process will be based on the following design tools:

- Design Entry and Simulation: Active HDL from Aldec or ModelSim Xilinx Edition from Xilinx,
- Logic Synthesis: Synplify Pro from Synopsys or Xilinx XST from Xilinx,
- Implementation: Xilinx ISE or Xilinx WebPACK from Xilinx.

The ASIC design process (front-end) will be based on the following design tools:

- Logic Synthesis: Design Compiler from Synopsys
- Timing Analysis: PrimeTime from Synopsys.

Hardware

Students will be required to purchase a Digilent Basys2 FPGA Board.

Required textbooks

Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience, 2008, ISBN: 978-0-470-18531-5.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill  © 3rd edition.

Recommended textbooks

  1. Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, ISBN 0-9669590-0-0, can be ordered from XESS Corporation Web Site (see also table of contents).
  2. Sunggu Lee, Advanced Digital Logic Design using VHDL, State Machines, and Syntesis for FPGAs, Thomson, 2006, ISBN: 0-534-46602-8.
     

Useful references

VHDL

VHDL Instructions: Templates & Examples

OpenCores Coding Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy
 

FPGAs & FPGA Boards

Documentation for Xilinx devices, and in particular for the Spartan 3E family

Digilent Basys2 FPGA Board

Xilinx ISE

Xilinx manuals for ISE software.


Related course web pages

ECE 448:    Spring 2009    Spring 2008    Spring 2007    Spring 2006

ECE 449:    Spring 2005    Spring 2004    Spring 2003

ECE 545:     Fall 2009 (with Dr. Gaj)   Fall 2008 (with Dr. Hwang)  Fall 2006 (with Dr. Gaj)


Exams & Quizzes from Previous Years

NEW!!! -   In-Class Midterm Exam from Spring 2010  - NEW!!!
Solutions: Task 1: bsm.vhd   Task 2: bsm_tb.vhd  Task 3: solution
In-Class Midterm Exam from Spring 2008
In-Class Midterm Exam from Spring 2007
Lab Midterm Exam from Spring 2007 - Tuesday Section
Lab Midterm Exam from Spring 2007 - Wednesday Section
 
Lab Midterm Exam from Spring 2008 - Tuesday Section
Lab Midterm Exam from Spring 2008 - Wednesday Section
Lab Midterm Exam from Spring 2008 - Thursday Section
 
Hands-on Midterm Exam from Spring 2004:
Solutions to the Midterm Exam - Tuesday section
Solutions to the Midterm Exam - Thursday section
 
Hands-on Midterm Exam from Spring 2005:
Solutions to the Midterm Exam - Monday section
Solutions to the Midterm Exam - Tuesday section
Solutions to the Midterm Exam - Thursday section
 
Practice Midterm Exam from Spring 2006
Practice Hands-on Midterm Exam
 
Practice Final Exam from Spring 2006
Practice final exam - Parts I & II
Solutions to Practice final exam - Part I
Solution to Part 2 Problem 3 - 2to1mux.vhd, 16to1mux.vhd
 
Quizzes from Spring 2006
Quiz 1
Quiz 2 with solutions
Quiz 3
Quiz 4 with solutions
Quiz 5 with solutions
 
Final Exam from Spring 2006
Final Exam Part I - version 1
Final Exam Part II - version 1
Final Exam Part I - version 2
Final Exam Part II - version 2
 
Final Exam from Spring 2007
Final Exam Part I - version 1
Final Exam Part II - version 1
Final Exam Part I - version 2
Final Exam Part II - version 2

 


Maintainer of the page: Kris Gaj