ECE 448

FPGA and ASIC Design with VHDL

Spring 2011

Quick Links

Instructor

Kris Gaj
The Nguyen Engineering Building, room 3225
e-mail:  kgaj (at) gmu.edu
             Please start a subject of your e-mail from "ECE 448:"
 

Teaching Assistants

Monday section

Mark Chaney
e-mail: mchaney_kns (at) yahoo.com

Tuesday section

Jeremy Kelly
e-mail: jeremy.a.kelly (at) gmail.com


Wednesday section

Ambarish Vyas
e-mail:  avyas2 (at) masonlive.gmu.edu


Thursday section

Ambarish Vyas
e-mail:  avyas2 (at) masonlive.gmu.edu

Lecture:

Tuesday, Thursday, 5:55-7:10PM, Enterprise Hall 276

Labs:

All Lab Sections meet 7:20-10:00 PM, The Nguyen Engineering Building, Room 3208.

All students will obtain access to the room 3208, and are welcome to work on their experiments at any time.
Experiment demonstrations will be accepted exclusively during the class time for a particular lab section.

Tentative list of office hours:

Saturday, 12:00-1:00 PM, Ambarish Vyas, Engineering 3208
Monday,     6:00-7:00 PM,
Jeremy Kelly, Engineering 3208
Monday,    10:00-11:00 PM, Mark Chaney, Engineering 3208
Tuesday,    1:00-2:00 PM, Ambarish Vyas, Engineering 3208
Tuesday,    4:30-5:30 PM, Kris Gaj, Engineering 3225
Wednesday,  1:00-2:00 PM, Ambarish Vyas, Engineering 3208
Thursday,    4:30-5:30 PM, Kris Gaj, Engineering 3225

All office hour sessions are open to all students, independently of their assignment to a particular lab section.

Course credit:

4 hours

Grading

Lab assignments (Part I):   20%
Midterm exam for the lecture:  10%
Midterm exam for the lab:  15%
Quizzes & homework  10%
Lab assignments (Part II):    20%
Final exam:  25%

General Laboratory Rules

Lecture slides (to be published before each lecture)

Primary Types of Problems to be Expected at the Part 2 of the Final Exam

Practice Final Exam - Part 1: Short Questions

Lecture 15: ASICs vs. FPGAs

Measuring the Gap Between FPGAs and ASICs (required reading)

Lecture 14: Overview of Modern FPGAs

Lecture 13: PicoBlaze I/O and Interrupt Interface

Lecture 12: PicoBlaze Overview

PicoBlaze 8-bit Embedded Microcontroller  User Guide for Spartan-3, Virtex-II, and Virtex-II Pro FPGA

KCPSM3 Manual

Lecture 11: Xilinx FPGA Memories

XAPP463 Using Block RAM in Spartan-3 Generation FPGAs

XAPP464 Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs

HDL Coding Techniques: RAM

XST User Guide, See Section: Coding Techniques

ISE In-Depth Tutorial, Section: Creating a CORE Generator Module

Lecture 10: RTL Design Methodology. Sorting Example. - extended with slides 15-16, April 13, 2011

    Sorting example

Lecture 9: Algorithmic State Machine (ASM) Charts

Lecture 8: RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram.

    Statistics example

Lecture 7: FPGA Devices.

Lecture 6: Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL code.

Lecture 5: Sequential-Circuit Building Blocks.

Lecture 4: Modeling of Circuits with Regular Structure. Constants, Aliases, Packages.

Lecture 3: Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic. - revised Feb. 9, 2011, 10am

Lecture 2: VHDL Refresher.

Lecture 1: Organization and Overview of the Course. Introduction to FPGA Technology.

Posted gradually typically one day before a given lecture.

See Course Webpage from Spring 2010 for slides from the previous year.
 

Homework assignments

        Special Homework Assignment - due Sunday, May 15, 11:59pm (15 extra credit quiz points)

Lab Assignments

Lab Assignment 6: Using PicoBlaze. Temperature Measurement. Serial Communication.

Lab Assignment 5: DSP and FPGA Embedded Resources. Signal Filtering and Display.

Lab Assignment 4: VGA Display. Bouncing Ball.

Lab Assignment 3: Sequential Logic for Synthesis. FPGA Design Flow. - updated Feb. 21, 2011, 1:30pm

Lab Assignment 2: Implementing Combinational Logic in VHDL. Simulation Using ModelSim.

Lab Assignment 1: Developing Effective Testbenches.

The specifications of lab assignments will be posted gradually here at least one day before a given assignment is introduced.

See Course Webpage from Spring 2010 for specifications of experiments from the previous year.

 

Lab Slides & Examples (to be published before each lab session)   

Lab Lecture 6: Using PicoBlaze. Temperature Measurement. Serial Communication.

Lab Lecture 5: DSP and FPGA Embedded Resources. Signal Filtering and Display.

Lab Lecture 4: VGA Display. Bouncing Ball.

Lab Lecture 3: Implementing Sequential Logic in VHDL. FPGA Design Flow based on Aldec Active-HDL.

Lab Lecture 2: Implementing Combinational Logic in VHDL. Simulation using ModelSim.

Lab Lecture 1: Developing Effective Testbenches. Simulation using Aldec Active HDL.

Lab slides and examples will be posted gradually at least one day before a given experiment is introduced.

See Course Webpage from Spring 2010 for slides from the previous year.


 

Software

The Detailed Instructions on How to Configure your FPGA Tools at School, and Install and Configure your FPGA Tools at Home

Introduction to Simulation with Aldec Active-HDL

Tutorial on FPGA Design Flow based on Aldec Active-HDL

Tutorial on FPGA Design Flow based on Xilinx ISE

Spartan-3E Libraries Guide for HDL Designs

Altera Quartus II Introduction for VHDL Users


The FPGA design process will be based on the following design tools:

- Design Entry and Simulation: Active HDL from Aldec, ModelSim PE Student Edition or ModelSim SE from Mentor Graphics
- Logic Synthesis: 
Xilinx XST from Xilinx or Synplify Pro from Synopsys
- Implementation: Xilinx ISE or Xilinx WebPACK from Xilinx.

Hardware

Students will be required to purchase a Digilent Basys2 FPGA Board.

Required textbooks

Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience, 2008, ISBN: 978-0-470-18531-5.

Recommended textbooks

  1. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill  © 3rd edition.
  2. Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, ISBN 0-9669590-0-0, can be ordered from XESS Corporation Web Site (see also table of contents).
  3. Sunggu Lee, Advanced Digital Logic Design using VHDL, State Machines, and Syntesis for FPGAs, Thomson, 2006, ISBN: 0-534-46602-8.
     

Useful references

VHDL

VHDL Instructions: Templates & Examples

OpenCores Coding Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy

Frequently Asked Questions about VHDL from comp.lang.vhdl
 

FPGAs & FPGA Boards

Documentation for Xilinx devices, and in particular for the Spartan 3E family

Digilent Basys2 FPGA Board

Xilinx ISE

Xilinx manuals for ISE software.


Related course web pages

ECE 448:   Spring 2010  Spring 2009    Spring 2008    Spring 2007    Spring 2006

ECE 449:    Spring 2005    Spring 2004    Spring 2003

ECE 545:     Fall 2010   Fall 2009   Fall 2008 (with Dr. Hwang)  Fall 2006


Exams & Quizzes from the Current and Previous Years

In-Class Midterm Exam from Spring 2011:    Group 1    Group 2    distribution of grades
Solutions for Group 1:  Problem 1, Problem 2: NFSR_1.vhd, F.vhd, NFSR_1_tb.vhd   Resource Utilization
Solutions for Group 2:  Problem 1, Problem 2: NFSR_2.vhd, F.vhd, NFSR_2_tb.vhd   Resource Utilization
 
In-Class Midterm Exam from Spring 2010
Solutions: Task 1: bsm.vhd   Task 2: bsm_tb.vhd  Task 3: solution
 
In-Class Midterm Exam from Spring 2009
In-Class Midterm Exam from Spring 2008
In-Class Midterm Exam from Spring 2007
 
Lab Midterm Exam from Spring 2011 - Monday Section
Solutions:  ma_ppd_pkg.vhd   ma_ppd.vhd   ma_ppd_tb.vhd
 
Lab Midterm Exam from Spring 2011 - Tuesday Section
Solutions:  to be posted soon
 
Lab Midterm Exam from Spring 2011 - Wednesday Section
Solutions:   regn.vhd   AV4.vhd   AV4_test.vhd
 
Lab Midterm Exam from Spring 2011 - Thursday Section
Solutions:  regn.vhd  full_adder.vhd  half_adder.vhd  madd.vhd  avg.vhd  avg_tb.vhd
 
Lab Midterm Exam from Spring 2010 - Monday Section
Solutions:   dgs.vhd   dgs_tb.vhd
 
Lab Midterm Exam from Spring 2010 - Tuesday Section
Solutions:   int-comb.vhd   cic.vhd   cic_tb.vhd
 
Lab Midterm Exam from Spring 2010 - Wednesday Section
Solutions:   grain128_pkg.vhd   grain128.vhd   grain128_tb.vhd
 
Lab Midterm Exam from Spring 2010 - Thursday Section
Solutions:   systolic_block.vhd   systolic_mult.vhd   systolic_mult_tb.vhd
 
Lab Midterm Exam from Spring 2007 - Tuesday Section
Lab Midterm Exam from Spring 2007 - Wednesday Section
 
Lab Midterm Exam from Spring 2008 - Tuesday Section
Lab Midterm Exam from Spring 2008 - Wednesday Section
Lab Midterm Exam from Spring 2008 - Thursday Section
 
Hands-on Midterm Exam from Spring 2004:
Solutions to the Midterm Exam - Tuesday section
Solutions to the Midterm Exam - Thursday section
 
Hands-on Midterm Exam from Spring 2005:
Solutions to the Midterm Exam - Monday section
Solutions to the Midterm Exam - Tuesday section
Solutions to the Midterm Exam - Thursday section
 
Practice Midterm Exam from Spring 2006
Practice Hands-on Midterm Exam
 
Practice Final Exam from Spring 2006
Practice final exam - Parts I & II
Solutions to Practice final exam - Part I
Solution to Part 2 Problem 3 - 2to1mux.vhd, 16to1mux.vhd
 
Quizzes from Spring 2006
Quiz 1
Quiz 2 with solutions
Quiz 3
Quiz 4 with solutions
Quiz 5 with solutions
 
Final Exam from Spring 2006
Final Exam Part I - version 1
Final Exam Part II - version 1
Final Exam Part I - version 2
Final Exam Part II - version 2
 
Final Exam from Spring 2007
Final Exam Part I - version 1
Final Exam Part II - version 1
Final Exam Part I - version 2
Final Exam Part II - version 2
 
Final Exam from Spring 2008
Final Exam Part I
Final Exam Part II
 
Final Exam from Spring 2009
Final Exam Part I
Final Exam Part II
 
Final Exam from Spring 2010
Final Exam Part I
Final Exam Part II

 

Maintainer of the page: Kris Gaj