ECE 448
FPGA and ASIC Design with
VHDL
Spring 2012
Final Exam will be held on
Tuesday, May 15, 4:30pm-7:15pm
in Robinson Hall B, room 228
Quick Links
Instructor
Kris Gaj
The Nguyen Engineering Building, room
3225
e-mail: kgaj (at) gmu.edu
Please
start a subject of your e-mail from "ECE 448:"
Teaching Assistants
Tuesday & Thursday
sections
Umar Sharif
e-mail: malik.umar.sharif (at) gmail.com
|
Wednesday section
Danesh
Esteki
e-mail: danesh.esteki (at) gmail.com
|
Lecture:
Tuesday,
Thursday, 5:55-7:10PM, Robinson Hall B, room 228
Labs:
All Lab
Sections meet 7:20-10:00 PM, The Nguyen Engineering Building,
Room 3208.
All
students will obtain access to the room 3208, and are welcome to work on
their experiments at any time.
Experiment demonstrations will be accepted exclusively
during the class time for a particular lab section.
Tentative list of office hours:
Saturday,
3:00-4:00 PM, Danesh Esteki, Engineering 3208
Monday, 1:00-3:00 PM, Umar
Sharif, Engineering 3208
Tuesday, 1:00-3:00 PM, Umar Sharif, Engineering
3208
Tuesday,
7:30-8:30 PM, Kris Gaj, Engineering 3225
Wednesday,
6:00-7:00
PM, Danesh Esteki, Engineering 3204
Thursday,
4:30-5:30 PM, Kris Gaj, Engineering 3225
All
office hour sessions are open to all students,
independently of their assignment to a particular lab section.
Course credit:
4
hours
Grading
| Lab
assignments
(Part I): |
20% |
| Midterm exam for the lecture: |
10% |
| Midterm exam for the lab: |
15% |
| Quizzes & homework |
10% |
| Lab
assignments
(Part II): |
20% |
| Final exam: |
25% |
General Laboratory Rules
- Each lab assignment will be preceded by an introduction and
a hands-on session taught by a TA.
- The deadlines for submitting all lab deliverables (including
source codes, diagrams, waveforms, configuration files, lab
reports, etc.) are being set as follows:
Tuesday section - Tuesday, 5:45 PM
Wednesday section - Wednesday, 5:45 PM
Thursday section - Thursday, 5:45 PM.
- Students will be required to demonstrate working experiment
during a lab session on a day designated as a due date for a
particular lab assignment.
- Experiment demonstrations will be accepted exclusively
during the class time for a particular lab section.
- For each lab assignment, the demonstration and the
electronic deliverables (including lab report) are each worth
50% of points allocated to a given lab assignment.
- Each lab assignment that is one week late will be penalized
by deducting 1/3 of its allocated points. No credit will be
received for a lab experiment that is more than one week late.
Opportunities will be provided to earn bonus points by
completing additional tasks for each assignment. Both penalty
and bonus points will apply independently to the
demonstrations and to the electronic deliverables.
- During the second part of the semester (after the Spring
break), the students can follow two schedules:
- Schedule A: Lab 5 - 2
weeks, Lab 6 - 2 weeks, Lab 7 - 2 weeks.
- Schedule B: Lab 5 - 3
weeks, Lab 6 - 3 weeks, Lab 7 not attempted.
Schedule B is intended for students who feel that they fall
behind, and need more time for Labs 5 and 6. These students
can avoid late submission penalties for Labs 5 and 6, but at
the same time, they have to give up their chance of earning
any points for Lab 7 (6 points). A decision about switching to
Schedule B, should be communicated to the respective lab
instructor no later than by the regular deadline for Lab 6
according to Schedule A.
- Office hours will be devoted to helping students with their
designs and answering any questions related to the subject of
the course.
- Students are required to work individually on most
assignments, unless group work is clearly stated in the text
of the assignment. In case of group work, all members of the
team are expected to be intimately familiar with the
entire solution to the given lab assignment and the entire
lab report. This knowledge will be verified during the
experiment demonstration and the same grade will be applied to
the entire team.
- Every completed experiment must be presented to your
TA, who will evaluate students results and effort. It is the
students' responsibility to convince the TA that their designs
work as required. Therefore, students have to simulate and
test their designs thoroughly and well document their work.
The TA is not required to test anything by himself nor to
investigate if the designs are correct in case of insufficient
documentation.
- In order to prevent cheating and plagiarism, the students
will be required to
- submit all electronic deliverables using Blackboard at the
designated time before the experiment demonstration,
- restrain from any changes in the experiment files in the
period between the electronic submission and the experiment
demonstration,
- answer correctly several detailed questions regarding their
solution at the time of demonstration.
Not complying with either of these requirements may lead to
either a total rejection of the demonstration by the TA, or to
a substantial reduction of the number of points awarded to the
student.
- In case of any evident attempt to submit somebody's else
work as your own, both students involved in the incident may
be penalized by taking away all points for the given lab
assignment. The two repeated attempts to present
somebody's else work as your own may lead to the F grade for
the entire course, independently of the total amount of points
earned by the student before the second incident.
- The students are encouraged to help and support each other
in all problems related to the
- operation of the CAD tools,
- operation of the FPGA boards,
- operation of the measurement equipment available in the lab,
- understanding of the problem to be solved during each
experiment.
Lecture slides (to
be published before each lecture)
Final Exam - general
types of problems that are likely to appear at the final exam
Grading Scheme,
including a typical final grade scale used in previous years
Lecture
14: Overview of Modern FPGAs
Lecture
13: PicoBlaze I/O & Interrupt Interface
Lecture
12: PicoBlaze Overview
Lecture 11:
Xilinx FPGA Memories
Lecture 10:
RTL Design Methodology. Statistics Example.
Lecture 9: RTL
Design Methodology. Sorting Example.
Lecture 8:
Modeling of Circuits with a Regular Structure.
Lecture 7:
FPGA Devices.
Lecture 6: Finite
State Machines. State Diagrams, State Tables, Algorithmic
State Machine (ASM) Charts and VHDL Code.
Lecture 5:
Modeling of Circuits with Regular Structure.
Lecture
4: Sequential-Circuit Building Blocks. - with
revised slides 33 & 35 (02/11/2012)
Lecture
3: Combinational-Circuit Building Blocks. Data Flow Modeling
of Combinational Logic.
Lecture
2: VHDL Refresher.
Lecture
1: Organization and Overview of the Course. Introduction to
FPGA Technology.
Posted gradually typically one day
before a given lecture.
See Course
Webpage from Spring 2011 for slides from the
previous year.
Homework assignments
Special Homework
Assignment - due Monday,
May 7, 11:59PM, submission using Blackboard
Posted gradually typically one week before a given homework
is due.
Lab Assignments
Lab Assignment 7: Using PicoBlaze.
Speed Punching.
Lab Assignment 6: DSP and FPGA
Embedded Resources. Digital Downconverter.
Lab Assignment 5: VGA Display.
Brick-breaker game.
Lab Assignment 4: Finite State
Machines. Bus Ticket Dispensing Machine.
Lab Assignment 3: Implementing
Sequential Logic in VHDL: Square Root Unit based on CORDIC.
Lab Assignment 2: Implementing
Combinational Logic in VHDL. Simulation Using Aldec
Active-HDL, ModelSim, and ISim.
Lab Assignment 1: Developing Effective
Testbenches.
The
specifications of lab assignments will be posted
gradually here at least one day before a given
assignment is introduced.
See Course
Webpage
from Spring 2011 for specifications of experiments
from the previous year.
Lab Slides & Examples (to be
published before each lab session)
Lab Lecture 7A: Troubleshooting and Data
Analysis Using Logic Analyzer.
Lab Lecture 7: Using PicoBlaze.
Speed Punching.
Lab Lecture 6: DSP and FPGA Embedded
Resources. Digital Downconverter.
Lab Lecture 5: VGA
Display. Brick-breaker game.
Lab Midterm Exam
Review
Lab Lecture 4: Finite
State Machines. FPGA Design Flow Based on Xilinx ISE and
ModelSim.
Lab Lecture 3:
Implementing Sequential Logic in VHDL. FPGA Design Flow
Based on Aldec Active HDL.
Lab Lecture 2:
Implementing Combinational Logic in VHDL. Simulation using
ModelSim and ISim.
Lab Lecture 1: Developing
Effective Testbenches. Simulation using Aldec Active
HDL.
Lab slides
and examples will be posted gradually at least one day
before a given experiment is introduced.
See Course
Webpage
from Spring 2011 for slides from the previous
year.
The Detailed
Instructions on How to Configure your FPGA
Tools at School, and Install and Configure
your FPGA Tools at Home,
last updated Feb. 4, 2012
Tutorial
on Simulation with Aldec Active-HDL, ver
2.6, Jan. 24, 2012
Tutorial
on Simulation with ModelSim, ver. 1.1, Feb. 1, 2012
Tutorial
on Simulation with ISim, ver 1.0, Feb. 1, 2012
Simulators
Reference Guide - covering Aldec Active-HDL,
ModelSim, and ISim, ver 1.0, Feb. 1, 2012
Tutorial
on FPGA Design Flow based on Aldec
Active-HDL, ver. 1.6, Oct. 22, 2011
Tutorial
on FPGA Design Flow based on Xilinx ISE and
ModelSim - ver. 1.7, Oct. 22, 2011
Tutorial
on Tutorial on Critical Path Analysis using
Synplify Premier DP, ver. 1.0, Nov. 18,
2011
Tutorial
on Troubleshooting and Data Analysis using
Logic Analyzer, ver. 1.0, May 2, 2012
The FPGA design process will be based on
the following design tools:
- Design Entry and Simulation: Active
HDL from Aldec, ModelSim
PE
Student Edition or ModelSim
SE from Mentor Graphics, and iSim
from Xilinx
- Logic Synthesis: Xilinx
XST from Xilinx
or
Synplify
Premier
DP from Synopsys
- Implementation: Xilinx
ISE or Xilinx
WebPACK from Xilinx.
|
Students
will be required to purchase a Digilent Basys2 FPGA Board.
Required
textbooks
Pong P. Chu,
FPGA
Prototyping
by VHDL Examples: Xilinx Spartan-3 Version,
Wiley-Interscience, 2008, ISBN: 978-0-470-18531-5.
Recommended
textbooks
- Stephen
Brown and Zvonko
Vranesic,
Fundamentals of Digital Logic
with VHDL Design, McGraw-Hill
© 3rd edition.
- Sundar Rajan, Essential
VHDL: RTL Synthesis Done Right, ISBN
0-9669590-0-0, can be ordered from XESS
Corporation Web Site (see also table
of contents).
- Sunggu Lee, Advanced Digital Logic Design using
VHDL, State Machines, and Syntesis for FPGAs,
Thomson, 2006, ISBN: 0-534-46602-8.
Useful
references
VHDL
VHDL
Instructions: Templates & Examples
OpenCores
Coding
Guidelines
The Low Carb
VHDL Tutorial - by Bryan Mealy
Frequently
Asked Questions about VHDL from comp.lang.vhdl
FPGAs & FPGA Boards
Documentation for Xilinx
devices, and in particular for the Spartan
3E family
Digilent Basys2 FPGA Board
Xilinx ISE
Xilinx
manuals for ISE software.
Related course web pages
ECE 448: Spring 2011 Spring 2010 Spring 2009 Spring
2008 Spring
2007 Spring
2006
ECE 449: Spring
2005 Spring
2004 Spring
2003
ECE
545: Fall 2011 Fall 2010 Fall
2009 Fall
2008 (with Dr. Hwang) Fall
2006
Exams &
Quizzes from the Current and Previous Years
In-Class
Midterm Exam from Spring 2012
|
| Solutions: Problem
1, Problem
2, Problem
3, Problem 4:
piso.vhd,
piso_inst.vhd
|
|
| In-Class
Midterm Exam from Spring 2011:
Group
1 Group
2 distribution
of
grades |
| Solutions for Group 1: Problem
1, Problem 2: NFSR_1.vhd,
F.vhd,
NFSR_1_tb.vhd
Resource
Utilization |
| Solutions for Group 2: Problem
1, Problem 2: NFSR_2.vhd,
F.vhd,
NFSR_2_tb.vhd
Resource
Utilization |
| |
| In-Class
Midterm
Exam from Spring 2010 |
| Solutions:
Task 1: bsm.vhd
Task 2: bsm_tb.vhd
Task 3: solution |
| |
| In-Class
Midterm
Exam from Spring 2009 |
|
In-Class
Midterm
Exam from Spring 2008 |
| In-Class
Midterm
Exam from Spring 2007 |
|
| Lab Midterm Exam from
Spring 2012 - Tuesday Section |
Solutions:
reg.vhd
shiftn.vhd
MidTerm_201.vhd
MidTerm_201_TB.vhd
Waveform.pdf
Report.pdf
|
|
| Lab Midterm
Exam from Spring 2012 -
Thursday Section |
Solutions:
reg.vhd
shift1.vhd
shiftn.vhd
counter.vhd
datapath.vhd
controller.vhd
MidTerm_203.vhd
MidTerm_203_TB.vhd
Waveform.pdf
Report.pdf
|
| |
| Lab Midterm
Exam from Spring 2011 - Monday
Section |
| Solutions:
ma_ppd_pkg.vhd
ma_ppd.vhd
ma_ppd_tb.vhd |
| |
| Lab
Midterm Exam from Spring 2011 - Tuesday
Section |
| Solutions:
to be posted soon |
| |
| Lab
Midterm Exam from Spring 2011 - Wednesday
Section |
| Solutions:
regn.vhd
AV4.vhd
AV4_test.vhd |
| |
| Lab Midterm Exam from
Spring 2011 - Thursday Section |
| Solutions: regn.vhd
full_adder.vhd
half_adder.vhd
madd.vhd
avg.vhd
avg_tb.vhd |
| |
| Lab Midterm
Exam from Spring 2010 - Monday
Section |
| Solutions:
dgs.vhd
dgs_tb.vhd |
| |
| Lab
Midterm Exam from Spring 2010 - Tuesday
Section |
| Solutions:
int-comb.vhd
cic.vhd
cic_tb.vhd |
| |
| Lab
Midterm Exam from Spring 2010 - Wednesday
Section |
| Solutions:
grain128_pkg.vhd
grain128.vhd
grain128_tb.vhd |
| |
| Lab Midterm Exam from
Spring 2010 - Thursday Section |
| Solutions:
systolic_block.vhd
systolic_mult.vhd
systolic_mult_tb.vhd
|
| |
| Lab Midterm Exam from Spring 2007 -
Tuesday Section |
| Lab Midterm Exam from Spring 2007 -
Wednesday Section |
| |
| Lab Midterm Exam from Spring 2008 -
Tuesday Section |
|
Lab Midterm Exam from Spring
2008 - Wednesday Section |
|
Lab Midterm Exam from Spring
2008 - Thursday Section |
| |
| Hands-on Midterm Exam from Spring 2004: |
| Solutions to the
Midterm Exam - Tuesday section |
| Solutions to the Midterm Exam
- Thursday section |
| |
| Hands-on
Midterm
Exam from Spring 2005: |
| Solutions to the Midterm Exam
- Monday section |
| Solutions to the Midterm Exam
- Tuesday section |
| Solutions to the Midterm Exam
- Thursday section |
| |
| Practice Midterm Exam from Spring 2006 |
| Practice
Hands-on
Midterm Exam |
| |
| Practice
Final
Exam from Spring 2006 |
| Practice
final
exam - Parts I & II |
| Solutions
to
Practice final exam - Part I |
| Solution to
Part 2 Problem 3 - 2to1mux.vhd,
16to1mux.vhd |
| |
| Quizzes from Spring 2006 |
| Quiz
1 |
| Quiz
2
with solutions |
| Quiz
3 |
| Quiz
4
with solutions |
| Quiz
5
with solutions |
| |
| Final
Exam
from Spring 2006 |
| Final
Exam
Part I - version 1 |
| Final
Exam
Part II - version 1 |
| Final
Exam
Part I - version 2 |
| Final
Exam
Part II - version 2 |
| |
| Final
Exam
from Spring 2007 |
| Final
Exam
Part I - version 1 |
| Final
Exam
Part II - version 1 |
| Final
Exam
Part I - version 2 |
| Final
Exam
Part II - version 2 |
| |
| Final Exam from
Spring 2008 |
| Final Exam Part I |
| Final Exam
Part II |
| |
| Final Exam from Spring 2009 |
| Final Exam
Part I |
| Final Exam
Part II |
| |
| Final Exam from Spring 2010 |
|
Final Exam Part I |
| Final
Exam Part II |
| |
| Final Exam from Spring 2011 |
Final Exam Part I - Group 1
|
Final Exam Part I - Group 2
|
| Final
Exam
Part II |
Solutions: P1_Block_diagram.jpg,
P2_ASM_chart.jpg,
P3_PicoBlaze_program.jpg
|
Maintainer of the page: Kris Gaj
