ECE 448

FPGA and ASIC Design with VHDL

Spring 2013


Quick Links

Instructor

Kris Gaj
The Nguyen Engineering Building, room 3225
e-mail:  kgaj (at) gmu.edu
             Please start a subject of your e-mail from "ECE 448:"
 

Teaching Assistant

Wednesday & Thursday sections
Umar Sharif
e-mail: malik.umar.sharif (at) gmail.com

Lecture:

Monday, Wednesday, 1:30-2:45 PM, Enterprise Hall, room 275

Labs:

Both Lab Sections meet 7:20-10:00 PM, The Nguyen Engineering Building, Room 3208.

All students will obtain access to the room 3208, and are welcome to work on their experiments at any time.
Experiment demonstrations will be accepted exclusively during the class time for a particular lab section.

Tentative list of office hours:

Umar Sharif, Engineering 3208:    

Kris Gaj, Engineering 3225:

All office hour sessions are open to all students, independently of their assignment to a particular lab section.

Course credit:

4 hours

Grading

Lab assignments (Part I):   20%
Midterm exam for the lecture:  10%
Midterm exam for the lab:  15%
Quizzes & homework  10%
Lab assignments (Part II):    20%
Final exam:  25%

General Laboratory Rules

Lecture slides (to be published before each lecture)


Final Exam - general types of problems that are likely to appear at the final exam

Grading Scheme, including a typical final grade scale used in previous years
 

Lecture 16: Design Methodology - sorting example. [PPT, PDF]

Lecture 15: Design Methodology - min_max_avr example. [PPT, PDF]

Lecture 14: PicoBlaze Instruction Set. [PPT, PDF]

Lecture 13: PicoBlaze I/O and Interrupt Interface. [PPT, PDF]

Lecture 12: PicoBlaze Overview. [PPT, PDF]

  Supplementary Reading:
Lecture 11: Xilinx FPGA Memories - Part 2 [PPT, PDF]

  Supplementary Reading:
Lecture 10: Xilinx FPGA Memories - Part 1. [PPT, PDF]

  Supplementary Reading:
Lecture 9: Modeling of Circuits with a Regular Structure. [PPT, PDF]

Lecture 8: VGA Display - Part 2. [PPT, PDF]  (extended 04/01)

Lecture 7: VGA Display - Part 1. [PPT, PDF]

Lecture 6: Finite State Machines: State Diagrams, State Tables, ASM Charts, and VHDL Code. [PPT, PDF]
(revised 02/27)

Lecture 5: FPGA Devices and FPGA Design Flow. [PPTX, PDF]

    Supplementary Reading: Spartan-6 FPGA Configurable Logic Block User Guide

Lecture 4: Sequential-Circuit Building Blocks. Mixing Description Styles. [PPT, PDF] (revised 02/15)

Lecture 3: Combinational-Circuit Building Blocks.Data Flow Modeling of Combinational Logic. [PPT, PDF]

Lecture 2: VHDL Refresher. [PPT, PDF]

Lecture 1: Organization and Overview of the Course. Introduction to FPGA Technology. [PPT, PDF]

Posted gradually typically one day before a given lecture.

See Course Webpage from Spring 2012 for slides from the previous year.
 

Homework assignments

      Posted gradually typically one week before a given homework is due.

Lab Assignments

Lab Assignment 8: Using PicoBlaze. Fast Sorting.

Lab Assignment 7: Design and Testing of an FIR Filter.

Lab Assignment 6: VGA Display. Collision Detection Game.

Lab Assignment 5: FPGA Design Flow Based on Aldec Active-HDL. Fast Reflex Game. (revised 02/28)

Lab Assignment 4: FPGA Design Flow Based on Xilinx ISE & ISim. 448_ (revised 02/28)

Lab Assignment 3: Implementing Sequential Logic in VHDL. Testing Digital Circuit.

Lab Assignment 2: Implementing Combinational Logic in VHDL. Advanced Testbenches.

Lab Assignment 1: Developing and Using Simple Testbenches.

The specifications of lab assignments will be posted gradually here at least one day before a given assignment is introduced.

See Course Webpage from Spring 2012 for specifications of experiments from the previous year.

 

Lab Slides & Examples (to be published before each lab session)   

Lab Lecture 8a: Troubleshooting and Data Analysis using Logic Analyzer

Lab Lecture 8: Using PicoBlaze. Fast Sorting.

Lab Lecture 7: Design and Testing of an FIR Filter.

Lab Lecture 6: VGA Display. Collision Detection Game.

Lab Lecture 5: FPGA Design Flow Based on Aldec Active-HDL. Fast Reflex Game.

Lab Lecture 4: FPGA Design Flow based on Xilinx ISE and ISim.

Lab Lecture 3: Implementing Sequential Logic in VHDL. Simulation Using ModelSim.

Lab Lecture 2: Implementing Combinational Logic in VHDL. Simulation Using Aldec Active-HDL.

Lab Lecture 1: Developing Effective Testbenches. Simulation using Xilinx ISim.

Lab slides and examples will be posted gradually at least one day before a given experiment is introduced.

See Course Webpage from Spring 2012 for slides from the previous year.


 

Software

The Detailed Instructions on How to Configure your FPGA Tools at School, and Install and Configure your FPGA Tools at Home ( last updated 09/19/2012)


Tutorial on Simulation with ISim (last updated 02/01/2012)

Tutorial on Simulation with Aldec Active-HDL (last updated 01/24/2012)

Tutorial on Simulation with ModelSim (last updated 02/01/2012)

Simulators Reference Guide - covering Aldec Active-HDL, ModelSim, and ISim (last updated 02/01/2012)


Tutorial on FPGA Design Flow based on Xilinx ISE and ISim (last updated 10/27/2012)

Tutorial on FPGA Design Flow based on Aldec Active-HDL (last updated 10/27/2012)

Tutorial on FPGA Design Flow based on Xilinx ISE and ModelSim (last updated 10/27/2012)

Tutorial on Critical Path Analysis using Synplify Premier DP (last updated 10/27/2012)

Tutorial on Troubleshooting and Data Analysis using Logic Analyzer (last updated 05/02/2012)


The FPGA design process will be based on the following design tools:

- Design Entry and Simulation: ISim from Xilinx, Active HDL from Aldec, ModelSim SE from Mentor Graphics
- Logic Synthesis: 
Xilinx XST from Xilinx or Synplify Premier DP from Synopsys
- Implementation: Xilinx ISE or Xilinx WebPACK from Xilinx.

Hardware

The boards will be distributed to the students for free by the TA during the lab sessions on February 20, 21. The boards should  be returned to the TA during the last lab sessions of the semester. In case the board you received appears to be out-of-order at the end of the semester, it will be your responsibility to replace it by a new board of the same type.

Alternatively, you can decide against using a departmental board, and purchase a board directly from Digilent Inc.


Required textbooks

Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience, 2008, ISBN: 978-0-470-18531-5.

Recommended textbooks

  1. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill  3rd edition.
  2. Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, ISBN 0-9669590-0-0, can be ordered from XESS Corporation Web Site (see also table of contents).
  3. Clive "Max" Maxfield, The Design Warrior's Guide to FPGAs: Devices, Tools and Flows. Newnes 2004.
     

Useful references

VHDL

VHDL Instructions: Templates & Examples

OpenCores Coding Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy

Frequently Asked Questions about VHDL from comp.lang.vhdl
 

FPGAs & FPGA Boards

Documentation for Xilinx devices, and in particular for the Spartan 6 family

Digilent Nexys3 FPGA Board

Xilinx ISE

Xilinx manuals for ISE software.


Related course web pages

ECE 448:   Spring 2012  Spring 2011   Spring 2010   Spring 2009    Spring 2008    Spring 2007    Spring 2006

ECE 449:    Spring 2005    Spring 2004    Spring 2003

ECE 545:     Fall 2012   Fall 2011   Fall 2010   Fall 2009   Fall 2008 (with Dr. Hwang)  Fall 2006


Exams & Quizzes from the Current and Previous Years

In-Class Midterm Exam from Spring 2013:
Text of the exam  Answer sheet   Solutions

In-Class Midterm Exam from Spring 2012
Solutions: Problem 1, Problem 2, Problem 3, Problem 4: piso.vhd, piso_inst.vhd

In-Class Midterm Exam from Spring 2011:    Group 1    Group 2    distribution of grades
Solutions for Group 1:  Problem 1, Problem 2: NFSR_1.vhd, F.vhd, NFSR_1_tb.vhd   Resource Utilization
Solutions for Group 2:  Problem 1, Problem 2: NFSR_2.vhd, F.vhd, NFSR_2_tb.vhd   Resource Utilization
 
In-Class Midterm Exam from Spring 2010
Solutions: Task 1: bsm.vhd   Task 2: bsm_tb.vhd  Task 3: solution
 
In-Class Midterm Exam from Spring 2009
In-Class Midterm Exam from Spring 2008
In-Class Midterm Exam from Spring 2007

Lab Midterm Exam from Spring 2013 - Wednesday Section
Solutions: regn.vhd  counter.vhd  lfsr.vhd  PISO.vhd  SIPO.vhd  midterm_wednesday.vhd  midterm_wednesday_TB.vhd  Functional_simulation_waveforms.pdf  Timing_simulations_waveforms_ISim.pdf  Timing_simulations_waveforms_Aldec.pdf  Tasks_4-6.pdf

Lab Midterm Exam from Spring 2013 - Thursday Section
Solutions: regn.vhd  counter.vhd  midterm_thursday.vhd  midterm_Thursday_TB.vhd  Functional_simulation_waveforms.pdf  Tasks_4-6.pdf

Lab Midterm Exam from Spring 2012 - Tuesday Section
Solutions: reg.vhd  shiftn.vhd  MidTerm_201.vhd  MidTerm_201_TB.vhd  Waveform.pdf  Report.pdf

Lab Midterm Exam from Spring 2012 - Thursday Section
Solutions: reg.vhd  shift1.vhd  shiftn.vhd  counter.vhd  datapath.vhd  controller.vhd  MidTerm_203.vhd  MidTerm_203_TB.vhd  Waveform.pdf  Report.pdf
 
Lab Midterm Exam from Spring 2011 - Monday Section
Solutions:  ma_ppd_pkg.vhd   ma_ppd.vhd   ma_ppd_tb.vhd
 
Lab Midterm Exam from Spring 2011 - Tuesday Section
 
Lab Midterm Exam from Spring 2011 - Wednesday Section
Solutions:   regn.vhd   AV4.vhd   AV4_test.vhd
 
Lab Midterm Exam from Spring 2011 - Thursday Section
Solutions:  regn.vhd  full_adder.vhd  half_adder.vhd  madd.vhd  avg.vhd  avg_tb.vhd
 
Lab Midterm Exam from Spring 2010 - Monday Section
Solutions:   dgs.vhd   dgs_tb.vhd
 
Lab Midterm Exam from Spring 2010 - Tuesday Section
Solutions:   int-comb.vhd   cic.vhd   cic_tb.vhd
 
Lab Midterm Exam from Spring 2010 - Wednesday Section
Solutions:   grain128_pkg.vhd   grain128.vhd   grain128_tb.vhd
 
Lab Midterm Exam from Spring 2010 - Thursday Section
Solutions:   systolic_block.vhd   systolic_mult.vhd   systolic_mult_tb.vhd
 
Lab Midterm Exam from Spring 2008 - Tuesday Section
Lab Midterm Exam from Spring 2008 - Wednesday Section
Lab Midterm Exam from Spring 2008 - Thursday Section

Lab Midterm Exam from Spring 2007 - Tuesday Section
Lab Midterm Exam from Spring 2007 - Wednesday Section
 
 
Hands-on Midterm Exam from Spring 2004:
Solutions to the Midterm Exam - Tuesday section
Solutions to the Midterm Exam - Thursday section
 
Hands-on Midterm Exam from Spring 2005:
Solutions to the Midterm Exam - Monday section
Solutions to the Midterm Exam - Tuesday section
Solutions to the Midterm Exam - Thursday section
 
Practice Midterm Exam from Spring 2006
Practice Hands-on Midterm Exam
 
Practice Final Exam from Spring 2006
Practice final exam - Parts I & II
Solutions to Practice final exam - Part I
Solution to Part 2 Problem 3 - 2to1mux.vhd, 16to1mux.vhd
 
Quizzes from Spring 2006
Quiz 1
Quiz 2 with solutions
Quiz 3
Quiz 4 with solutions
Quiz 5 with solutions
 
Final Exam from Spring 2006
Final Exam Part I - version 1
Final Exam Part II - version 1
Final Exam Part I - version 2
Final Exam Part II - version 2
 
Final Exam from Spring 2007
Final Exam Part I - version 1
Final Exam Part II - version 1
Final Exam Part I - version 2
Final Exam Part II - version 2
 
Final Exam from Spring 2008
Final Exam Part I
Final Exam Part II
 
Final Exam from Spring 2009
Final Exam Part I
Final Exam Part II
 
Final Exam from Spring 2010
Final Exam Part I
Final Exam Part II
 
Final Exam from Spring 2011
Final Exam Part I - Group 1
Final Exam Part I - Group 2
Final Exam Part II 
Solutions: P1_Block_diagram.jpg, P2_ASM_chart.jpg, P3_PicoBlaze_program.jpg

Final Exam from Spring 2012
Final Exam Part I - Group 1
Final Exam Part I - Group 2
Final Exam Part II
Solutions: P1_1.jpg, P1_2.jpg, P2.jpg, P3_Task1_1.jpg, P3_Task1_2.jpg, P3_Task2.pdf

Quizzes from Spring 2013
Quiz_1
Quiz_2, Quiz_2_solutions
Quiz_3, Quiz_3_solutions

Final Exam from Spring 2013: Part 1, Part 2
Solutions: Part 1, Part 2

 

Maintainer of the page: Kris Gaj