ECE 448
FPGA and ASIC Design with VHDL
Spring 2015
Quick Links
Organization
Lecture
Lab
Instructor
Kris Gaj
The Nguyen Engineering Building, room 3225
email: kgaj (at) gmu.edu
Please start a subject of your email from "ECE 448:"
Teaching
Assistants
Monday and Wednesday section:
Umar Sharif
email: malik.umar.sharif (at) gmail.com
Thursday section:
Rabia Shahid
email: rabia.shahid4 (at) gmail.com
Lecture and Lab Time
Lecture:
Monday, Wednesday, 1:302:45 PM, Robinson Hall A, room 412
Labs:
Monday,
4:307:10pm, Engineering
Building, Room 3208
Wednesday, 7:2010:00pm, Engineering
Building, Room 3208
Thursday, 7:2010:00pm, Engineering
Building, Room 3208
All students will obtain access to the ECE Labs 3208 and 3204, and are welcome to work on their
experiments at any time.
Experiment demonstrations will be accepted exclusively during
the class time for a particular lab section.
Office Hours:
Umar Sharif:
 Monday, 12:001:00pm, Engineering 3204
 Wednesday, 4:005:00pm, Engineering 3204
 Thursday, 5:007:00pm, Engineering 3231
Rabia Shahid:
 Tuesday, 4:006:00pm, Engineering 3203
 Thursday, 2:004:00pm, Engineering 3204
Kris Gaj:
 Monday, 3:004:00pm, Engineering 3225
 Wednesday, 3:004:00pm, Engineering 3225
 Thursday, 6:007:00pm, Engineering 3225
All office hour sessions are open to all students, independently of their
assignment to a particular lab section.
Course credit:
4 hours
Grading
Lab assignments (Part I): 
20% 
Midterm exam for the
lecture: 
10% 
Midterm exam for the lab: 
15% 
Quizzes & homework 
10% 
Lab assignments (Part II): 
20% + 2% bonus 
Final exam: 
25% 
Lecture
Textbooks
Required textbooks
Pong P. Chu,
FPGA Prototyping by VHDL Examples: Xilinx Spartan3
Version, WileyInterscience, 2008, ISBN: 9780470185315.
Recommended textbooks
 Stephen
Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design,
McGrawHill © 3rd
edition.
 Clive
"Max" Maxfield, The Design Warrior's Guide to FPGAs: Devices, Tools
and Flows, Newnes 2004
Lecture Slides
Final Exam Exercise:
text
analysis
block diagram
ASM chart
Final Exam  general
types of problems that are likely to appear on the final exam
Lecture 18  PicoBlaze Instruction Set & Assembler Directives.
[ppt,
pdf]
Lecture 17  PicoBlaze I/O & Interrupt Interface.
[ppt,
pdf]
Lecture 16  PicoBlaze Overview.
[ppt,
pdf]
Lecture 15  RTL Design Methodology. Part II: SORTING Example.
[ppt,
pdf]
Lecture 14  RTL Design Methodology. Part I: STATISTICS Example.
[ppt,
pdf]
Lecture 13  VGA Display. Part 5: The Complete Pong Game.
[ppt,
pdf]
Lecture 12  VGA Display. Part 4: Text Generation.
[ppt,
pdf]
Lecture 11  VGA Display. Part 3: Animation.
[ppt,
pdf]
Lecture 10  VGA Display. Part 2: Pixel Generation.
[ppt,
pdf]
Lecture 9  VGA Display. Part 1: VGA Synchronization.
[ppt,
pdf]
Lecture 8  Modeling of Circuits with Regular Structure. [ppt, pdf]
Lecture 7  Algorithmic State Machine (ASM) Charts: VHDL Code and Timing Diagrams [ppt, pdf]
Lecture 6  Finite State Machines. State Diagrams vs.
Algorithmic State Machine (ASM) Charts. [ppt, pdf]
Lecture 5  FPGA Devices & FPGA Design Flow. [ppt, pdf]
Lecture 4  SequentialCircuit Building Blocks. Constants & Packages. Mixing Description
Styles. [ppt, pdf]
Lecture 3  CombinationalCircuit Building Blocks. Data Flow
Modeling of Combinational Logic. [ppt, pdf]
Lecture 2  VHDL Refresher [ppt, pdf]
Lecture 1  Objectives, Scope, and Organization of the Course
[ppt,
pdf]
Posted gradually typically one day before a given lecture.
See Course Webpage from Spring 2014 for slides from the
previous year.
Homework
Posted gradually typically one week before a
given homework is due.
Labs
General Laboratory Rules
 Each lab assignment will be preceded by an introduction and a handson session
taught by a TA.
 The deadlines for submitting
all lab deliverables (including source codes, diagrams, waveforms,
configuration files, lab reports, etc.) are being set as
follows:
Monday section  Monday, 4:00 PM
Wednesday section  Wednesday, 7:00 PM
Thursday section  Thursday, 7:00 PM.
 Students will be required to demonstrate working experiment during a lab session on a
day designated as a due date for a particular lab assignment.
 Experiment demonstrations will be accepted exclusively during the class
time for a particular lab section.
 For each lab assignment, the demonstration and the electronic deliverables
(including lab report) are each worth 50% of points allocated to a
given lab assignment.
 Each lab assignment that is one week late will be penalized by deducting 1/3 of
its allocated points. No credit will be received for a lab experiment
that is more than one week late. Opportunities will be provided to earn
bonus points by completing additional tasks for each assignment. Both
penalty and bonus points will apply independently to the demonstrations
and to the electronic deliverables.
 During the
second part of the semester (after the Spring break), the students can
follow two schedules:
 Schedule A: Lab 4  2
weeks, Lab 5  2 weeks, Lab 6  2 weeks.
 Schedule B: Lab 4  3 weeks, Lab 5 or
Lab 6  3 weeks. One lab is not attempted, and
as a result its grade is set to 0.
Schedule B is intended for students who feel that they fall behind, and
need more time for Labs 46. These students can avoid late submission
penalties, but at the same time, they have to give up their chance of
earning points for one of the two last labs, Lab 5 or Lab 6 (6 points).
A decision about switching to Schedule B, should be communicated to the
respective lab instructor no later than by the regular deadline for Lab
4 according to Schedule A.
 Students who do well in Labs 13 can sign up for Schedule A+.
This schedule will involve working on an openended
project proposed by the students, the TA , or the instructor.
The project can be done individually or in groups of two
students. The schedule of the project must include the following
steps:
 draft specification
 Spring break
week
 revised specification approved by the instructor and the TA  1
week
 milestone 1  2
weeks
 milestone 2  2
weeks
 final report & deliverables  1 week.
 Office hours will be devoted to helping students with their designs
and answering any questions related to the subject of the course.
 Students are required to work individually on most assignments,
unless group work is clearly stated in the text of the assignment. In
case of group work, all members of the team are expected to be
intimately familiar with the entire solution to the given lab
assignment and the entire lab report. This knowledge
will be verified during the experiment demonstration and the same grade
will be applied to the entire team.
 Every completed experiment must be presented to the TA, who will
evaluate students' results and effort. It is the student's
responsibility to convince the TA that their designs work as required.
Therefore, students have to simulate and test their designs thoroughly
and well document their work. The TA is not required to test anything
by himself nor to investigate if the designs are correct in case of
insufficient documentation.
 In order to prevent cheating and plagiarism, the students will be
required to
 submit all electronic deliverables using Blackboard at the
designated time before the experiment demonstration,
 restrain from any changes in the experiment files in the period
between the electronic submission and the experiment
demonstration,
 answer correctly several detailed questions regarding their
solution at the time of demonstration.
Not complying with either of these requirements may lead to either
a total rejection of the demonstration by the TA, or to a
substantial reduction of the number of points awarded to the
student.
 In case of any evident attempt to submit somebody's else work as
your own, both students involved in the incident may be penalized by
taking away all points for the given lab assignment. The
two repeated attempts
to present somebody's else work as your own may lead to the F grade for
the entire course, independently of the total amount of points earned
by the student before the second incident.
 The students are encouraged to help and support each other in all
problems related to the
 operation of the CAD tools,
 operation of the FPGA boards,
 operation of the measurement equipment available in the lab,
 understanding of the problem to be solved during each experiment.
Lab Assignments
Lab Assignment 6: Using PicoBlaze. Speed Punching Game.
Lab Assignment 5: Mandelbrot Fractal Viewer.
Lab Assignment 4: VGA Display.
The Frogger.
Lab Assignment 3: Finite State Machines.
Automated Teller Machine.
Lab Assignment 2: Implementing
Combinational and Sequential Logic in VHDL.  with Fig. 3 revised on 02/09/2015
Lab Assignment 1: Developing Effective
Testbenches.
The specifications of lab assignments will be posted gradually here
at least one day before a given assignment is introduced.
See Course Webpage from Spring 2014 for specifications of
experiments from the previous year.
Lab Lecture 7: Troubleshooting and Data Analysis using Logic
Analyzer
Lab Lecture 6: Using PicoBlaze. Speed Punching Game.
Lab Lecture 5: Mandelbrot Set Fractal.
Lab Lecture 4: VGA Display.
The Frogger.
Lab Lecture 3: FPGA Design Flow.
Using SevenSegment Displays, Buttons, and Switches. Design of
Controllers Using FSMs.
Lab Lecture 2: Implementing
Combinational and Sequential Logic in VHDL. Simulation using Aldec
ActiveHDL.
Lab Lecture 1: Developing Effective
Testbenches. Simulation using Xilinx ISim.
Lab slides and examples will be posted gradually at least one
day before a given experiment is introduced.
See Course Webpage from Spring 2014 for lab slides
from the previous year.
The boards will be distributed to the students for free by the
TA during the lab sessions in the fourth or fifth week of the
semester. The boards should be returned to the TA during the last
lab sessions of the semester. In case the board you received
appears to be outoforder at the end of the semester, it will be
your responsibility to replace it by a new board of the same
type.
Alternatively, you can decide against using a departmental
board, and purchase a board directly from Digilent Inc.
Useful
References
VHDL
VHDL Instructions: Templates &
Examples
OpenCores Coding
Guidelines
The Low Carb VHDL Tutorial  by Bryan
Mealy
Frequently Asked Questions about VHDL from
comp.lang.vhdl
FPGAs & FPGA
Boards
Documentation for Xilinx FPGA devices, and in particular for the
Spartan 6 family
Digilent
Nexys3 FPGA
Board
Xilinx ISE
Xilinx manuals for ISE
software.
Related course web pages:
ECE 448:
Spring 2013 Spring
2012
Spring
2011 Spring 2010 Spring 2009 Spring 2008 Spring 2007 Spring 2006
ECE 449:
Spring 2005 Spring 2004 Spring 2003
ECE 545:
Fall 2013
Fall 2012
Fall 2011 Fall 2010 Fall 2009 Fall
2006
Past
Exams
Past Lab
Exams
Past
Quizzes
Past Midterm Exams
InClass
Midterm Exam from Spring 2015:

Text of the
exam Answer
sheet Solutions

Source Codes:
Controller (Problems 1 & 4):
controller.vhd
controller_tb.vhd
Variable Arithmetic Shifter Right (Problem 3):
fixed_shifter_right.vhd
variable_shifter_right.vhd
variable_shifter_right_tb.vhd


InClass
Midterm Exam from Spring 2014:

Text of the
exam


InClass
Midterm Exam from Spring 2013:

Text of the
exam Answer
sheet Solutions


InClass Midterm
Exam from Spring 2012

Solutions: Problem
1, Problem
2, Problem
3, Problem 4: piso.vhd,
piso_inst.vhd 

InClass Midterm
Exam from Spring 2011: Group 1
Group 2
distribution
of grades 
Solutions for
Group 1: Problem
1, Problem 2: NFSR_1.vhd,
F.vhd,
NFSR_1_tb.vhd
Resource Utilization 
Solutions for
Group 2: Problem
1, Problem 2: NFSR_2.vhd,
F.vhd,
NFSR_2_tb.vhd
Resource Utilization 

InClass Midterm Exam from Spring
2010

Solutions: Task 1: bsm.vhd Task 2:
bsm_tb.vhd
Task 3: solution 

InClass
Midterm Exam from Spring
2009

InClass
Midterm Exam from Spring 2008 
InClass Midterm Exam from Spring 2007 

Handson Midterm Exam from Spring 2004: 
Solutions to the Midterm
Exam  Tuesday section

Solutions to the Midterm Exam 
Thursday section 

Handson
Midterm Exam from Spring 2005: 
Solutions to the Midterm Exam 
Monday section 
Solutions to the Midterm Exam 
Tuesday section 
Solutions to the Midterm Exam 
Thursday section 

Practice Midterm Exam from Spring 2006 
Practice Handson Midterm Exam 
Past Final Exams
Practice
Final Exam from Spring 2006 
Practice final exam  Parts
I & II 
Solutions to Practice final
exam  Part I 
Solution to
Part 2 Problem 3 
2to1mux.vhd,
16to1mux.vhd 

Final Exam
from Spring 2006 
Final Exam Part
I  version 1

Final Exam Part
II  version 1

Final Exam Part
I  version 2

Final Exam Part
II  version 2


Final Exam
from Spring 2007 
Final Exam Part I  version 1

Final Exam Part II  version 1

Final Exam Part
I  version 2

Final Exam Part II  version 2 

Final Exam from Spring
2008 
Final
Exam Part I

Final
Exam Part II


Final Exam from Spring
2009 
Final
Exam Part I

Final
Exam Part II


Final Exam from Spring 2010 
Final Exam Part I

Final Exam Part II


Final Exam from Spring 2011 
Final Exam Part I  Group 1

Final Exam Part I  Group 2

Final Exam
Part II 
Solutions: P1_Block_diagram.jpg,
P2_ASM_chart.jpg,
P3_PicoBlaze_program.jpg


Final Exam
from Spring 2012 
Final Exam Part I  Group
1

Final Exam
Part I  Group 2

Final Exam
Part II

Solutions: P1_1.jpg,
P1_2.jpg,
P2.jpg,
P3_Task1_1.jpg,
P3_Task1_2.jpg,
P3_Task2.pdf


Final Exam
from Spring 2013:
Part 1,
Part 2

Solutions:
Part 1,
Part 2


Final Exam
from Spring 2014:
Part 1,
Part 2
