Kris Gaj
The Nguyen Engineering Building, room 3225
email: kgaj (at) gmu.edu
Please start a subject of your email from "ECE 448:"
Sanjay Deshpande
email: sdeshpan (at) masonlive.gmu.edu
Please start a subject of your email from "ECE 448:"
Monday, Wednesday, 1:302:45 PM, Innovation Hall, room 204
Monday, 4:307:10pm, Engineering Building, Room 3208
Tuesday, 9:0011:40am, Engineering Building, Room 3208
Wednesday, 7:2010:00pm, Engineering Building, Room 3208
All students will obtain access to the ECE Labs 3208 and 3204, and are welcome to work on their experiments at any time.
Experiment demonstrations will be accepted exclusively during the class time for a particular lab section.
Sanjay Deshpande:
 Monday, 11:00am1:00pm, Engineering 3204
 Wednesday, 11:00am12:00pm, Engineering 3204
Kris Gaj:
All office hour sessions are open to all students, independently of their assignment to a particular lab section.
 Monday, 3:004:00pm, Engineering 3225
 Wednesday, 3:004:00pm, Engineering 3225
 Thursday, 6:007:00pm, Engineering 3225
4 hours
Lab assignments (Part I): 20% Midterm exam for the lecture: 10% Midterm exam for the lab: 15% Quizzes & homework 10% Lab assignments (Part II): 20% + 2% bonus Final exam: 25%
Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan3 Version, WileyInterscience, 2008, ISBN: 9780470185315.
 Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGrawHill © 3rd edition.
 Clive "Max" Maxfield, The Design Warrior's Guide to FPGAs: Devices, Tools and Flows, Newnes 2004
Final Exam  general types of problems that are likely to appear on the final exam
Lecture 19  RTL Design Methodology. Part II: SORTING Example. [ppt, pdf]
Lecture 18  PicoBlaze Instruction Set & Assembler Directives. [ppt, pdf]
Lecture 16  PicoBlaze I/O & Interrupt Interface. [ppt, pdf] (revised on 04/21 to include solutions to the class exercise)
Lecture 15  PicoBlaze Overview. [ppt, pdf]
Lecture 14  RTL Design Methodology. Part I: STATISTICS Example. [ppt, pdf]
Lecture 13  VGA Display. Part 5: The Complete Pong Game. [ppt, pdf]
Lecture 12  VGA Display. Part 4: Text Generation. [ppt, pdf]
Lecture 11  VGA Display. Part 3: Animation. [ppt, pdf]
Lecture 10  VGA Display. Part 2: Pixel Generation. [ppt, pdf]
Lecture 9  VGA Display. Part 1: VGA Synchronization. [ppt, pdf]
Lecture 8  Modeling of Circuits with Regular Structure. [ppt, pdf]
Lecture 7  Algorithmic State Machine (ASM) Charts: VHDL Code and Timing Diagrams [ppt, pdf]
Lecture 6  Finite State Machines. State Diagrams vs. Algorithmic State Machine (ASM) Charts. [ppt, pdf]
Lecture 4  SequentialCircuit Building Blocks. Constants & Packages. Mixing Description Styles. [ppt, pdf]
Lecture 3  CombinationalCircuit Building Blocks. Data Flow Modeling of Combinational Logic. [ppt, pdf]
Lecture 2  VHDL Refresher [ppt, pdf]
Lecture 1  Objectives, Scope, and Organization of the Course [ppt, pdf]
Posted gradually, typically one day before a given lecture.
See Course Webpage from Spring 2015 for slides from the previous year.
Special Homework
Assignment  due Saturday, May 7, 11:59pm.
 draft specification  Spring break week
 revised specification approved by the instructor and the TA  1 week
 milestone 1  2 weeks
 milestone 2  2 weeks
 final report & deliverables  1 week.
Lab Assignment 6: Using PicoBlaze. Fast Sorting.
Lab Assignment 5: Julia Set Fractal Viewer.
Lab Assignment 4: VGA Display. Snake Game.
Lab Assignment 3: Finite State Machines. Movie Ticket Dispensing Machine.
Lab Assignment 2: Implementing Combinational and Sequential Logic in VHDL.
Lab Assignment 1: Developing Effective Testbenches.
The specifications of lab assignments will be posted gradually here at least one day before a given assignment is introduced.
See Course Webpage from Spring 2015 for specifications of experiments from the previous year.
Lab Lecture 7: Troubleshooting and Data Analysis using Logic Analyzer
Lab Lecture 6: Using PicoBlaze. Fast Sorting.
Lab Lecture 5: Julia Set Fractal.
Lab Lecture 4: VGA Display. Snake Game.
Lab Lecture 1: Developing Effective Testbenches. Simulation using Xilinx ISim.
Lab slides and examples will be posted gradually at least one day before a given experiment is introduced.
See Course Webpage from Spring 2015 for lab slides from the previous year.
Please see Tutorials
available on the page: Tutorials
and Lab Manuals. Use "448" or "ECE 448" as a filter. The FPGA design process will be based on the following design tools:

 Digilent Nexys 3 FPGA Board
 Digilent Nexys 4 DDR FPGA Board
 Digilent Nexys 3 Board Reference Manual
 Digilent Nexys 4 DDR FPGA Board Reference Manual
 Digilent Adept
 Spartan6 FPGA Family
 Artix7 FPGA Family
 Spartan6 FPGA User Guides
 Artix7 FPGA Family User Guides
 Digital oscilloscopes, Tektronics TDS 224, 100 MHz bandwidth, 1GS/s sample rate, 4 channels
 Agilent logic analyzer
FPGA boards will be distributed to the students for free by the TA during the lab sessions in the fourth or fifth week of the semester. The boards should be returned to the TA during the last lab sessions of the semester. In case the board you received appears to be outoforder at the end of the semester, it will be your responsibility to replace it by a new board of the same type.
Alternatively, you can decide against using a departmental board, and purchase a board directly from Digilent Inc.
VHDL
VHDL Instructions: Templates & Examples
The Low Carb VHDL Tutorial  by Bryan Mealy
Frequently Asked Questions about VHDL from comp.lang.vhdl
Xilinx ISE
Xilinx tutorials and user guides for ISE software.
Related course web pages:
ECE 448: Spring 2015 Spring 2014 Spring 2013 Spring 2012 Spring 2011 Spring 2010 Spring 2009
ECE 545: Fall 2015 Fall 2014 Fall 2013 Fall 2012 Fall 2011 Fall 2010 Fall 2009
Past Lab Exams
Past Midterm Exams
InClass Midterm Exam from Spring 2015:
Text of the exam Answer sheet Solutions
Source Codes:
Controller (Problems 1 & 4): controller.vhd controller_tb.vhd
Variable Arithmetic Shifter Right (Problem 3): fixed_shifter_right.vhd variable_shifter_right.vhd variable_shifter_right_tb.vhd
InClass Midterm Exam from Spring 2014:
Text of the exam
InClass Midterm Exam from Spring 2013:
Text of the exam Answer sheet Solutions
InClass Midterm Exam from Spring 2012
Solutions: Problem 1, Problem 2, Problem 3, Problem 4: piso.vhd, piso_inst.vhd
InClass Midterm Exam from Spring 2011: Group 1 Group 2 distribution of grades Solutions for Group 1: Problem 1, Problem 2: NFSR_1.vhd, F.vhd, NFSR_1_tb.vhd Resource Utilization Solutions for Group 2: Problem 1, Problem 2: NFSR_2.vhd, F.vhd, NFSR_2_tb.vhd Resource Utilization InClass Midterm Exam from Spring 2010 Solutions: Task 1: bsm.vhd Task 2: bsm_tb.vhd Task 3: solution InClass Midterm Exam from Spring 2009 InClass Midterm Exam from Spring 2008
Past Final Exams
Final Exam from Spring 2008 Final Exam Part I Final Exam Part II Final Exam from Spring 2009 Final Exam Part I Final Exam Part II Final Exam from Spring 2010 Final Exam Part I Final Exam Part II Final Exam from Spring 2011 Final Exam Part I  Group 1
Final Exam Part I  Group 2
Final Exam Part II Solutions: P1_Block_diagram.jpg, P2_ASM_chart.jpg, P3_PicoBlaze_program.jpg
Final Exam from Spring 2012 Final Exam Part I  Group 1 Final Exam Part I  Group 2
Final Exam Part II
Solutions: P1_1.jpg, P1_2.jpg, P2.jpg, P3_Task1_1.jpg, P3_Task1_2.jpg, P3_Task2.pdf
Final Exam from Spring 2013: Part 1, Part 2
Solutions: Part 1, Part 2
Final Exam from Spring 2014: Part 1, Part 2
Final Exam from Spring 2015: Part 1, Part 2