ECE 545
Digital System Design with VHDL

Fall 2009

Time and location:    Wednesday, 7:20-10:00 PM, Robinson Hall B, room 205

Instructor:                  Kris Gaj  
Email:                         kgaj@gmu.edu
Office hours:              Monday, Tuesday, Wednesday, 6:00-7:00 PM
                                    The Engineering Building, room 3225

TA:                              "Ice" - Ekawat Homsirikamol
Email:                          ehomsiri@gmu.edu
Office hours:              Tuesday, Wednesday, 5:00-6:00 PM
                                    The Engineering Building, room 3204
 

Please submit all your homework and project reports using Blackboard by going to http://courses.gmu.edu

 

Course Description

Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis and performance optimization. Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs. 

Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly recommended.

 

Required Textbooks

Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006.

 

Supplementary Textbooks

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Edition, McGraw-Hill, 2008.

Volnei A. Pedroni, Circuit Design with VHDL, The MIT Press, 2004.

Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998.

Peter J. Ashenden, The Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann Publishers, 2008.
 

Software Packages Used in This Class

  • Aldec Active HDL
  • Mentor Graphics ModelSim
  • ModelSim Xilinx Edition III
  • Synplicity Synplify Pro
  • Xilinx XST
  • Xilinx ISE
  • Xilinx WebPACK
  • Altera Quartus II
  • GMU ATHENa

All software will be available in the Computer Engineering Lab, The Engineering Building, room 3208.
Selected software can be installed on your laptops and home workstations.

Projects

NEW!!! - ATHENa Download Page - NEW!!!

NEW!!! - ATHENa Tutorial - NEW!!!

NEW!!! - ATHENa Main Page - NEW!!!

NEW!!! - ATHENa and Project Deliverables - NEW!!!

NEW!!! - Tentative Solutions to A Simple SHA Controller Example (zip format) (last update,  Thursday, Dec. 10, 7:15 AM) - NEW!!!

NEW!!! - Padding Script and Comprehensive Testbench for Testing all SHA-3 Candidates - NEW!!!

NEW!!! - SHA-3 Interface and Timing Analysis with Two Clocks - NEW!!!

NEW!!! - SHA-3 Candidate Evaluation - highlights, steps of the design process, FPGA performance measures - NEW!!!

NEW!!!Specification of AES, including mathematical background and comprehensive test vectors - NEW!!!

Project - Phase 4: specification of tasks + usuful recommendations

Project - Phase 3: specification of tasks + usuful recommendations

Project - Phase 2: specification of tasks + usuful recommendations

Hardware Interface of a Secure Hash Algorithm (SHA)

SHA-3 Hardware Implementations by Other Groups

The SHA-3 Zoo

This year's project will involve implementing a selected cryptographic hash function competing in the contest for a new American hash standard SHA-3.
The list and specification of remaining SHA-3 candidates is available here. Each student will design, implement, and optimize one algorithm assign to him/her by the instructor. All implementations will be optimized using multiple criteria and implemented using multiple families of FPGAs from Xilinx and Altera. This project will support NIST in selection of a hash algorithm most suitable from the point of view of  hardware efficiency.

Homework

Homework 1 - due Saturday, October 10, 11:59PM, using Blackboard

Test Vectors for Homework 1 - ver. 1 - corrected Wednesday, Oct. 7, 6:30pm

Waveforms for Homework 1 - ver. 1 - posted Monday, Oct. 5, 11:30pm

Test Vectors for Homework 1 - ver. 2 - posted Wednesday, Oct. 7, 6:30pm

Waveforms for Homework 1 - ver. 2 - posted Wednesday, Oct. 7, 6:30pm

Solutions to Homework 1:   hw1circuit.vhd    hw1circuit_tb.vhd

Homework assignments will be posted gradually here, at least 6 days before a given assignment's due date.

Viewgraphs

Lecture 1 - Organization of the Course

Lecture 2 - FPGA Devices and FPGA Design Flow

Lecture 3 - Digital Logic Review

Lecture 4 - Introduction to VHDL for Synthesis

Lecture 5 - Simple Testbenches

Lecture 6 - Dataflow Modeling of Combinational Logic

Lecture 7 - Modeling of Arithmetic Circuits

Lecture 8 - Behavioral Modeling of Sequential-Circuit Building Blocks

Lecture 9 - RTL Design Methodology - updated on Saturday, Oct. 17, 7:30pm

    Example 1: MIN_MAX_AVR    Example 2: Sorting

Lecture 10 - Parameterized Design: Modeling of Circuits with a Regular Structure

Lecture 12 - Advanced Testbenches

Lecture 13 - Memories

Lecture 14 - Design of Controllers. Finite State Machine and Algorithmic State Machine (ASM) Charts.

NEW!!! - Lecture 15 - Describing Combinational Logic Using Processes - NEW!!!

NEW!!! - ATHENa and Project Deliverables - NEW!!!

NEW!!! - Follow-up Courses - NEW!!!

Viewgraphs will be posted gradually here, at least one day before a given lecture.

 

Reference Material

VHDL

VHDL Instructions: Templates & Examples

OpenCores HDL modeling guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy

 

Tools

The Detailed Instructions on How to Configure your FPGA Tools at School, and Install and Configure your FPGA Tools at Home (last updated 8/20/2009)

Tutorial on Simulation using Aldec Active-HDL (last updated 09/21/2009)

Tutorial on FPGA Design Flow based on Aldec Active-HDL (to be updated)

Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim (to be updated)

Tutorial on Concurrent Version System based on CVS NT and Tortoise CVS (to be updated)


Past Course Web Pages

ECE 545:     Fall 2008 (with Dr. Hwang)   Fall 2006 (with Dr. Gaj)

ECE 448:     Spring 2009 (with Dr. Gaj)

 

Practice and Past Exams

NEW !!! - Midterm Exam 2009 - NEW!!!

NEW !!! - Solutions to the Midterm Exam 2009: Task 1  Task 2  Task 3  Task 4 - NEW!!!

Midterm Exam 2009: Recommended Reading and Practice Problems

Practice Midterm Exam

Solutions to the Practice Midterm Exam


Midterm Exam 1 from Fall 2006

Midterm Exam 1 from Fall 2005

Midterm Exam 1 from Fall 2004

 

Midterm Exam 2 from Fall 2006

Midterm Exam 2 from Fall 2005

Midterm Exam 2 from Fall 2004