Time and location:
Wednesday, 7:20-10:00 PM, Robinson Hall B, room 205
Instructor: Kris
Gaj
Email: kgaj@gmu.edu
Office hours:
Monday,
Tuesday, Wednesday, 6:00-7:00 PM
The Engineering Building, room 3225
TA:
"Ice"
- Ekawat Homsirikamol
Email:
ehomsiri@gmu.edu
Office hours:
Tuesday, Wednesday, 5:00-6:00 PM
The
Engineering Building, room 3204
Please
submit all your homework and
project reports using Blackboard by
going to http://courses.gmu.edu
Course Description
Introduces the design of
complex digital
systems using hardware description languages. Teaches design
methodologies which partition a system into a datapath and controller.
Focuses on synthesizable RTL VHDL code for digital circuit design using
dataflow, structural, and behavioral coding styles. Introduces VHDL
simulation and verification, and FPGA synthesis, placement, routing,
timing analysis and performance optimization. Requires semester-long
project devoted to the design of a complex digital system implemented
on FPGAs.
Prerequisites: Graduate
Standing. No official course prerequisite is required, but an
undergraduate background in digital logic design is strongly
recommended.
Required Textbooks
Pong
P. Chu, RTL
Hardware Design Using VHDL: Coding for Efficiency, Portability, and
Scalability,
Wiley-IEEE Press, 2006.
Supplementary Textbooks
Stephen Brown and
Zvonko
Vranesic, Fundamentals
of Digital Logic with VHDL Design,
3rd Edition, McGraw-Hill, 2008.
Volnei A. Pedroni,
Circuit Design with VHDL, The
MIT Press, 2004.
Sundar Rajan, Essential
VHDL:
RTL Synthesis Done Right,
S & G Publishing, 1998.
Peter
J. Ashenden, The
Designer's Guide to VHDL,
3rd
Edition, Morgan Kaufmann Publishers, 2008.
Software Packages Used in This Class
- Aldec Active HDL
- Mentor Graphics ModelSim
- ModelSim Xilinx Edition III
- Synplicity Synplify Pro
- Xilinx XST
- Xilinx ISE
- Xilinx WebPACK
- Altera Quartus II
- GMU ATHENa
All
software will be
available in the Computer Engineering Lab, The Engineering Building,
room 3208.
Selected software can be installed on your laptops and home
workstations.
Projects
- Datapath: Block Diagram
(last
update, Thursday, Dec. 10, 7:15 AM)
- Datapath: VHDL code: datapath.vhd,
pack.vhd, shiftin.vhd,
shiftout.vhd, countern.vhd
(last update, Wednesday, Dec. 9, 10:00
AM)
- FSM
1 -
input: ASM chart
(last
update, Wednesday, Dec. 9, 1:00 AM)
- FSM 1 - VHDL code:
fsm1.vhd (last update, Wednesday,
Dec. 9, 10:00 AM)
- FSM
2 -
processing: ASM chart
(last
update, Wednesday,
Dec. 9, 1:00 AM)
- FSM 2 - VHDL code:
fsm2.vhd (last update, Wednesday,
Dec. 9, 10:00 AM)
- FSM
3 -
output: ASM chart (last
update, Wednesday, Dec. 9, 1:00 AM)
- FSM 3 - VHDL code:
fsm3.vhd (last update, Wednesday,
Dec. 9, 10:00 AM)
- Counters
used in FSMs 1, 2, 3 - Block Diagram (last
update, Wednesday,
Dec. 9, 1:00 AM)
- Full
Controller: Exchange of information among FSMs 1, 2, 3 (last
update, Wednesday, Dec. 9, 1:00 AM)
- Full Controller - VHDL
code: top_fsm.vhd (last
update, Wednesday, Dec. 9, 10:00 AM)
- Status Registers used for
Communication between FSMs (last
update, Wednesday, Dec. 9, 1:00 AM)
- Status
Register & Clock Synchronization Circuit - VHDL code: sr_reg.vhd,
sync_clock.vhd (last
update, Wednesday, Dec. 9, 10:00 AM)
- Top
Level Circuit - top.vhd (last
update, Wednesday, Dec. 9, 10:00 AM)
- Testbench - VHDL code: fifo_ram.vhd,
fifo.vhd, sha_tb.vhd,
input.txt, out.txt
(last
update, Wednesday, Dec. 9, 10:00 AM)
NEW!!!
- Padding
Script and Comprehensive Testbench for Testing all SHA-3 Candidates
-
NEW!!!
This year's project will
involve
implementing a selected cryptographic hash function competing in the
contest for a new American hash standard SHA-3.
The list and specification of remaining SHA-3 candidates is available here.
Each student will design, implement, and optimize one algorithm assign
to him/her by the instructor. All implementations will be optimized
using multiple criteria and implemented using multiple families of
FPGAs from Xilinx and Altera. This project will support NIST in
selection of a hash algorithm most suitable from the point of view of
hardware efficiency.
Homework
Homework
1 - due
Saturday, October 10, 11:59PM, using Blackboard
Homework
assignments will
be posted gradually here, at least 6 days before a given assignment's
due
date.
Viewgraphs
Viewgraphs
will be posted gradually
here, at least one day before a given
lecture.
Reference Material
VHDL
VHDL
Instructions: Templates & Examples
OpenCores
HDL modeling guidelines
The
Low
Carb VHDL Tutorial - by Bryan
Mealy
Tools
Past Course Web
Pages
ECE 545:
Fall
2008
(with Dr. Hwang) Fall
2006
(with Dr. Gaj)
ECE 448:
Spring 2009
(with Dr. Gaj)
Practice
and Past Exams
NEW
!!! - Solutions to the Midterm
Exam 2009: Task
1 Task
2 Task
3 Task
4 -
NEW!!!
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