library ieee;
use ieee.std_logic_1164.all;  	 
use ieee.numeric_std.all;
use work.pack.all;

entity rc5_tb is
	generic (
		r : integer := 2;		
		W : integer := 16;	
		LW : integer := 4;
		MM : integer := 3
	);
end rc5_tb;

architecture tb of rc5_tb is
	-- inputs
	signal clk : std_logic := '0';
	signal reset, write_M, write_Si : std_logic;
	signal M : std_logic_vector((2*W)-1 downto 0);
	signal Si : std_logic_vector(W-1 downto 0);
	signal i : std_logic_vector(MM-1 downto 0);
	
	--outputs
	signal C : std_logic_vector((2*W)-1 downto 0);
	signal Done : std_logic;
	
	
	-- constant
	constant clk_period : time := 50 ns;  -- clk_period
	
	constant MSG : std_logic_vector((2*W)-1 downto 0) := x"0000ABCD";
	type s_type is array ( 0 to 5 ) of std_logic_vector(W-1 downto 0);
	signal s : s_type := (x"B134", x"5634", x"5347", x"4728", x"4923", x"90BC");
begin
	rc5_gen : rc5 generic map ( r => r, W => W, LW => LW, MM => MM ) 
	port map ( 	clk => clk, reset => reset, 
					M => M, write_M => write_M,   --msg
					Si => Si, write_Si => write_Si, i => i, 		 -- key
					C => C, Done => Done );
	
	clk <= not clk after clk_period /2;
	
	tb : process
	begin			
		write_M <= '0'; write_Si  <= '0';
		reset <= '1';
		wait for 2*clk_period;
		reset <= '0';
		wait for clk_period;
		-- key loading
		write_Si <= '1';
			
		for j in 0 to 5 loop	   
			Si <= s(j);
			i <= std_logic_vector(to_unsigned(j, MM) );	
			wait for clk_period;
		end loop;	  
		write_Si <= '0';
		
		-- msg loading
		
		write_M <= '1';
		M <= MSG;
		wait for clk_period;
		write_M <= '0';
		wait for clk_period;
		
		-- finished
		
		wait;
		
	end process;
	
	
end tb;