Homework 1
due Saturday, October 10, 11:59 pm
submission using Blackboard
Problems
a. Describe a circuit shown in the diagram below using synthesizable
VHDL.
b. Write a testbench capable of
verifying the operation of this circuit for a single key, single
initialization vector , and a message of the size of at least 32 bytes.
c. Synthesize your circuit using Xilinx XST (called from Aldec
Active-HDL or from Xilinx WebPACK/ISE). Use the smallest and fastest
device of the Spartan 3 family capable of holding your circuit. Please
note that this device can be determined by the maximum number
of user inputs/outputs. Do your best to remove any potential
errors and at least majority of warnings. Analyze the contents
of the report files.
d. Perform post-synthesis simulation of your circuit and make sure that
this simulation returns exactly the same results as functional
simulation.
e. Implement your circuit using Xilinx tools. Do your best to remove
any potential errors and at least majority of warnings. Analyze the
contents of of the report files.
f. Perform timing simulation of your circuit and make sure that
this simulation returns the same logical values, as functional
simulation, for a clock frequency close to
the maximum clock frequency of the analyzed circuit after placing &
routing.
g. Perform static timing analysis and determine the most critical path
in your circuit. Mark this path in your block diagram.
h. Optimize your circuit for maximum clock frequency using options of
tools and/or changes in your VHDL code.
i. Report the following data after optimization:
- FPGA device used
- minimum clock period after synthesis
- maximum clock frequency after synthesis
- minimum clock period after placing & routing
- maximum clock frequency after placing & routing
- number of CLB slices
- number of LUTs
- number of flip-flops
- number of I/O blocks
- all non-default options of tools
- logic components included in the critical path.
What to Turn In:
Submit the following files using Blackboard. DO NOT submit
your entire Aldec or Xilinx project with all its files, directories,
subdirectories, temp files, etc.; only submit what is requested below.
- All synthesizable source codes (before and after optimization for
speed)
- Testbench
- Create a text file called hw1_results_basic.txt and . In the text
file, give a short summary including:
- A. FPGA device, non-default options of tools
- B. Results after synthesis: #slices, #flip-flops, #LUTs,
#IOs, maximum clock frequency, minimum period. If your synthesis tool
only gives slices instead of LUTs (or vice-versa) after synthesis, just
note this in your text file.
- C. Results after implementation: #slices, #flip-flops, #LUTs,
#IOs, maximum clock frequency, minimum period
- D. logic components included in the critical path.
- Synthesis report
- Netlist rtl schematic
- Full implementation report(s)
- Static timing analysis report
- Waveforms from simulation before synthesis (in .awf format for
Active HDL or .wlf format for ModelSim)
- Waveforms from simulation post-synthesis (in .awf format for
Active HDL) or post-translate (in .wlf format for ModelSim)
- Waveforms from timing simulation post place-and-route (in .awf
format for Active HDL or .wlf format for ModelSim)