library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; 

entity hw1circuit is
	port ( 
		clk : in std_logic;
		-- control signals
		run 	: in std_logic;
		shift 	: in std_logic;
		init 	: in std_logic;
		-- data in
		key		: in std_logic_vector(63 downto 0);
		IV		: in std_logic_vector(63 downto 0);
		msg		: in std_logic_vector(3 downto 0);
		-- data out
		cph		: out std_logic_vector(3 downto 0)
	);	  
end hw1circuit;

architecture arch of hw1circuit is
	-- register signals 
	signal msg_regout, cph_regin : std_logic_vector(3 downto 0);
	signal key_regout : std_logic_vector(63 downto 0); 
	
	-- shift register	 
	signal shift_regout, shift_temp : std_logic_vector(63 downto 0);
	
	-- square components
	signal pe, po, odd, neg : std_logic;
	signal pe_pre, po_pre, odd_pre, neg_pre : std_logic_vector(15 downto 0);
	signal pe_pre1, pe_pre2, po_pre1, po_pre2 : std_logic;
	
begin
	
	-- REGISTERS
	msgreg : process ( clk )
	begin				  
		if rising_edge( clk ) then
			if ( run = '1' ) then
				msg_regout <= msg;
			end if;
		end if;
	end process;			
	
	cphreg : process ( clk )
	begin
		if rising_edge( clk ) then
			if ( shift = '1' ) then
				cph <= cph_regin;
			end if;
		end if;
	end process;  
	
	keyreg : process ( clk )
	begin
		if rising_edge( clk ) then
			if ( init = '1' ) then
				key_regout <= key;
			end if;
		end if;
	end process;				  
	
	shift4reg : process( clk )
	begin
		if rising_edge( clk ) then
			if ( init = '1' ) then
				shift_temp <= IV;
			elsif ( shift = '1' ) then
				shift_temp <= shift_temp(59 downto 0) & cph_regin;
			end if;
		end if;
	end process;
	shift_regout <= shift_temp;
	
	-- before box
	pe_pre <= shift_regout(63 downto 48) xor key_regout(63 downto 48);
	po_pre <= std_logic_vector(unsigned(shift_regout(47 downto 32)) + unsigned(key_regout(47 downto 32)));
	odd_pre <= std_logic_vector(signed(key_regout(31 downto 16)) - signed(shift_regout(31 downto 16)));
	neg_pre <= shift_regout(15 downto 0) xor key_regout(15 downto 0);
	
	-- box
		-- generate an odd parity bit (you can do a generate loop to do this)
	po_pre1 <= ((po_pre(0) xor po_pre(1)) xor (po_pre(2) xor po_pre(3))) xor ((po_pre(4) xor po_pre(5)) xor (po_pre(6) xor po_pre(7)));
	po_pre2 <= ((po_pre(8) xor po_pre(9)) xor (po_pre(10) xor po_pre(11))) xor ((po_pre(12) xor po_pre(13)) xor (po_pre(14) xor po_pre(15)));
	po <= po_pre1 xor po_pre2;
		-- generate an even parity bit
	pe_pre1 <= ((pe_pre(0) xor pe_pre(1)) xor (pe_pre(2) xor pe_pre(3))) xor ((pe_pre(4) xor pe_pre(5)) xor (pe_pre(6) xor pe_pre(7)));
	pe_pre2 <= ((pe_pre(8) xor pe_pre(9)) xor (pe_pre(10) xor pe_pre(11))) xor ((pe_pre(12) xor pe_pre(13)) xor (pe_pre(14) xor pe_pre(15)));
	pe <= not ( pe_pre1 xor pe_pre2 );		
		-- odd
	odd <= odd_pre(0);
		--neg
	neg <= neg_pre(15);
	
	-- after box
	cph_regin <= msg_regout xor ( pe & po & odd & neg );
	
end arch;