library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE ieee.std_logic_textio.all;

LIBRARY std;
USE std.textio.all;		

entity hw1circuit_tb is
end hw1circuit_tb;

architecture TB_ARCHITECTURE of hw1circuit_tb is
	-- Component declaration of the tested unit
	component hw1circuit
	port(
		clk : in STD_LOGIC;	   
		run : in STD_LOGIC;
		shift : in STD_LOGIC;
		init : in STD_LOGIC;
		key : in STD_LOGIC_VECTOR(63 downto 0);
		IV : in STD_LOGIC_VECTOR(63 downto 0);
		msg : in STD_LOGIC_VECTOR(3 downto 0);
		cph : out STD_LOGIC_VECTOR(3 downto 0) );
	end component;
	
	-- inputs
	constant msg_val : std_logic_vector(255 downto 0) := x"0123456789ABCDEFFEDCBA98765432100123456789ABCDEFFEDCBA9876543210"; -- msg from left to right
	constant key_val : std_logic_vector(63 downto 0) := x"0123456789ABCDEF";
	constant IV_val : std_logic_vector(63 downto 0) 	 := x"FEDCBA9876543210";
	
	constant encryption_size : integer := 256; -- encryption size in bits (must be multiple of half a byte)
	constant nibble_no : integer := encryption_size/4; -- number of half a byte
	-- clk period
	constant cpr : time := 20 ns; 

	-- output file
	FILE fileout	: TEXT OPEN WRITE_MODE   is  "testvector.txt";
	
	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clk : STD_LOGIC := '0';			 			 
	signal run : STD_LOGIC;
	signal shift : STD_LOGIC;
	signal init : STD_LOGIC;	
	
	signal key : STD_LOGIC_VECTOR(63 downto 0) := key_val;
	signal IV : STD_LOGIC_VECTOR(63 downto 0) := IV_VAL;
	signal msg : STD_LOGIC_VECTOR(3 downto 0);
	-- Observed signals - signals mapped to the output ports of tested entity
	signal cph : STD_LOGIC_VECTOR(3 downto 0);
	

begin

	-- Unit Under Test port map
	UUT : hw1circuit
		port map ( 
			clk => clk,
			run => run,
			shift => shift,
			init => init,
			key => key,
			IV => IV,
			msg => msg,
			cph => cph
		);
	
	clk <= not clk after cpr / 2;
	
	shift <= not init; -- shift always is not init (assume no additional msg is processed afterward);
	
	tb : process
		variable run_cycle : integer;		 
		variable bin_line, hex_line : line;
	begin	
		-- writing inputs
		write ( hex_line, "Input:" );
		writeline( fileout, hex_line);
		write ( hex_line, "BINARY_MSG = " );
		write ( hex_line,  msg_val );
		writeline( fileout, hex_line);	
		write ( hex_line, "HEX_MSG = " );
		hwrite ( hex_line,  msg_val );
		writeline( fileout, hex_line);		
		write ( hex_line, "BINARY_IV = " );
		write ( hex_line,  iv_val );
		writeline( fileout, hex_line);	
		write ( hex_line, "HEX_IV = " );
		hwrite ( hex_line,  iv_val );
		writeline( fileout, hex_line);			
		write ( hex_line, "BINARY_KEY = " );
		write ( hex_line,  key_val );
		writeline( fileout, hex_line);	
		write ( hex_line, "HEX_KEY = " );
		hwrite ( hex_line,  key_val );
		writeline( fileout, hex_line);	
		writeline( fileout, hex_line);
		write ( hex_line, "Output:" );
		writeline( fileout, hex_line);
		-- writing output
		write( bin_line, "BINARY_OUTPUT = " );
		write( hex_line, "HEX_OUTPUT = " );
		
		run_cycle := nibble_no;
		init <= '0'; 
		run <= '0';
		wait for cpr*2;
		init <= '1';  
		wait for cpr*2;
		run <= '1';					
		msg <= msg_val( (run_cycle*4)-1 downto (run_cycle-1)*4);
		wait for cpr;
		init <= '0';		
		while ( run_cycle > 0 ) loop
			msg <= msg_val( (run_cycle*4)-1 downto (run_cycle-1)*4);
			wait for cpr;			
				write( bin_line, cph );
				hwrite( hex_line, cph );
			run_cycle := run_cycle - 1;
		end loop;					   
		
		writeline( fileout, bin_line );
		writeline( fileout, hex_line );	   
		writeline( fileout, hex_line);

		
		wait for cpr*10;
		report "TB FINISHED" severity failure;
		wait; 
	end process;
	
	
	
end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_hw1circuit of hw1circuit_tb is
	for TB_ARCHITECTURE
		for UUT : hw1circuit
			use entity work.hw1circuit(arch);
		end for;
	end for;
end TESTBENCH_FOR_hw1circuit;