library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.pack.all;
entity datapath is					
	port (
		--external
		clk : in std_logic;
		io_clk: in std_logic;	  		
		din : in std_logic_vector(63 downto 0);
		dout : out std_logic_vector(63 downto 0);
		--FSM1
		ein : in std_logic; 
		lc : in std_logic;
		ec : in std_logic;
		
		zc256 : out std_logic; 
		zc0 : out std_logic;
		
		-- FSM2
		si : in std_logic;
		er : in std_logic;
		lo : in std_logic;
		sf : in std_logic;
		
		-- FSM3
		eo : in std_logic;
		--top fsm
		last_fast_clock_cycle : in std_logic
		
	);
end datapath;			   

architecture struct of datapath is
    signal rprime_temp : std_logic_vector(260 downto 0);																		
	signal mux1out, mux2in, mux2out, r, rin, rprime : std_logic_vector(255 downto 0);
	
	signal c : std_logic_vector(63 downto 0);		
	signal eout : std_logic;	  
begin	
	--- Counters required in different FSM		 
	
	
	--- ================ MAIN DATAPATH							  
	shfin_gen : shiftin generic map (N => 256, M => 64) port map (clk => io_clk, en => ein, input => din, output => rin );

	-- block decounter
	decounter_gen : process ( io_clk )
	begin
		if rising_edge( io_clk ) then
			if ( lc = '1' ) then
				c <= din;
			elsif ( ec = '1' ) then
				c <= c - 256;
			end if;
		end if;
	end process;	
	zc0 <= '1' when c = 0 else '0';
	zc256 <= '1' when c = 256 else '0';
	
	-- mux			   
	mux1out <= rprime when sf = '0' else (others => '0');
	mux2in <= mux1out xor rin;
    mux2out <= mux2in when si = '1' else rprime;
		
	-- state register
	state_reg_gen : process ( clk )
	begin
		if rising_edge(clk) then
			if ( er = '1' ) then
				r <= mux2out;
			end if;
		end if;
	end process;
	
	-- operation
	rprime_temp <= "10000"*r;
	rprime <= rprime_temp(255 downto 0);	  
	
	-- output							
	eout <= eo or (lo and last_fast_clock_cycle);
	shfout_gen : shiftout generic map (N => 256, M => 64) port map (clk => io_clk, sel => lo, en => eout, input => rprime, output => dout );
	
end struct;