library ieee;
use ieee.std_logic_1164.all;  
use ieee.std_logic_unsigned.all;

entity fifo is
	generic (
	  DEPTH : integer :=256;	
	  LOG2DEPTH : integer := 8;
	  N : integer := 64);
	port (
	  clk, rst: in std_logic;
	  wr_en, rd_en: in std_logic;
	  datain : in std_logic_vector(N-1 downto 0);
	  dataout : out std_logic_vector(N-1 downto 0);
	  fifo_full, fifo_empty : out std_logic);
end fifo;

architecture behavioral of fifo is


	component	fifo_ram is
		generic ( 	DEPTH 		: integer := 512;
					LOG2DEPTH  	: integer := 9;
					N	 		: integer := 64 );	
	    Port ( 	clk : in  STD_LOGIC;
				wr_en : in std_logic;
	           	rd_addr : in  STD_LOGIC_VECTOR (LOG2DEPTH-1 downto 0);
				wr_addr : in  STD_LOGIC_VECTOR (LOG2DEPTH-1 downto 0);
	    		din : in  STD_LOGIC_VECTOR (N-1 downto 0);
	           	dout : out  STD_LOGIC_VECTOR (N-1 downto 0));
	end component;


	signal readpointer  : std_logic_vector(LOG2DEPTH-1 downto 0);
	signal writepointer : std_logic_vector(LOG2DEPTH-1 downto 0);
	signal bytecounter  : std_logic_vector(LOG2DEPTH downto 0);	   
	signal ones : std_logic_vector(LOG2DEPTH-1 downto 0);	   
	
	signal wr_en_s : std_logic;
	signal fifo_full_s    : std_logic;
	signal fifo_empty_s   : std_logic;
	signal dataout_s : std_logic_vector(N-1 downto 0);

begin		 
	
	fiforam: fifo_ram
	generic map(
		DEPTH => DEPTH,
		LOG2DEPTH => LOG2DEPTH,
		N => N
	)
	port map(
			clk => clk,
			wr_en => wr_en_s,
			wr_addr => writepointer,
			rd_addr => readpointer,
			din => datain,
			dout => dataout
	);	

	process(clk,rst)
	begin
		if (rst = '1') then
			readpointer  <= (others => '0');
			writepointer <= (others => '0'); 
			bytecounter  <= (others => '0');  --differences (write pointer - read pointer)
		elsif(clk'event and clk = '1') then
			if ( wr_en = '1' and fifo_full_s = '0' and rd_en = '0') then
				writepointer <= writepointer + 1;
				bytecounter  <= bytecounter + 1;
			elsif ( rd_en = '1' and fifo_empty_s = '0' and wr_en = '0') then
				readpointer  <= readpointer + 1;
				bytecounter  <= bytecounter - 1;
			elsif ( rd_en = '1' and fifo_empty_s = '0' and wr_en = '1' and fifo_full_s = '0') then
				readpointer <= readpointer + 1;
				writepointer <= writepointer + 1;
			elsif ( rd_en = '1' and fifo_empty_s = '0' and wr_en = '1' and fifo_full_s = '1') then	-- cant write
				readpointer <= readpointer + 1;
				bytecounter <= bytecounter - 1;
			elsif ( rd_en = '1' and fifo_empty_s = '1' and wr_en = '1' and fifo_full_s = '0') then -- cant read
				writepointer <= writepointer + 1;
				bytecounter <= bytecounter + 1;
			end if;
		end if;
	end process;

	fifo_empty_s <= '1' when (bytecounter = 0) else  '0';
	fifo_full_s  <= bytecounter(LOG2DEPTH);

	fifo_full  <= fifo_full_s;
	fifo_empty <= fifo_empty_s;

	wr_en_s <= '1' when ( wr_en = '1' and fifo_full_s = '0') else '0';

end behavioral;