----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:00:29 11/15/2008 
-- Design Name: 
-- Module Name:    fifo_ram - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fifo_ram is
	 generic ( 	DEPTH 		: integer := 512;
					LOG2DEPTH  	: integer := 9;
					N 		: integer := 64 );	
    Port ( 	clk : in  STD_LOGIC;
			wr_en : in std_logic;
    	    rd_addr : in  STD_LOGIC_VECTOR (LOG2DEPTH-1 downto 0);
		   	wr_addr : in  STD_LOGIC_VECTOR (LOG2DEPTH-1 downto 0);
           	din : in  STD_LOGIC_VECTOR (N-1 downto 0);
           	dout : out  STD_LOGIC_VECTOR (N-1 downto 0));
end fifo_ram;

architecture Behavioral of fifo_ram is
	type mem is array (DEPTH-1 downto 0) of std_logic_vector(N-1 downto 0);
	signal memory : mem;
    --signal tmp_addr : std_logic_vector(LOG2DEPTH-1 downto 0);
begin
	process(clk)
	begin
		if ( rising_edge(CLK) ) then
			if (wr_en = '1') then
				memory(conv_integer(unsigned(wr_addr))) <= din;
			end if;
			--tmp_addr <= rd_addr;	 
		end if;
	end process; 
	--dout <= memory(conv_integer(unsigned(tmp_addr)));
	dout <= memory(conv_integer(unsigned(rd_addr)));
end Behavioral;