library ieee;
use ieee.std_logic_1164.all;

package pack is
	component shiftout is
		generic ( 
			N	: integer := 512;	--inputs
			M	: integer := 32		--outputs -- N must be divisible by M
		);
		port (
			clk 	 : in std_logic;
			en   : in std_logic;
			sel	 : in std_logic;
			input  : in std_logic_vector(N-1 downto 0);
			output : out std_logic_vector(M-1 downto 0)
		);
	end component;
	
	component shiftin is
		generic ( 
			N	: integer := 512;
			M	: integer := 32		-- N must be divisible by M
		);
		port (
			clk 	 : in std_logic;				 
			en     : in std_logic;
			input  : in std_logic_vector(M-1 downto 0);
			output : out std_logic_vector(N-1 downto 0)
		);
	end component;
	
	component countern is
		generic ( 
		    N : integer := 2
		);
		port ( 	  
		   	    clk : in std_logic;
	    load : in std_logic;
	    en : in std_logic; 
		input  : in std_logic_vector(N-1 downto 0);
        output : out std_logic_vector(N-1 downto 0)
		);
	end component; 
	
	component sr_reg is							
		port (					
			rst			: in std_logic;
			clk 		: in std_logic;
			set     	: in std_logic;
			clr         : in std_logic;
			output		: out std_logic
		);				 
	end component;
	
	component fsm1 is
		port (
		io_clk : in std_logic;
		rst : in std_logic;		
		
		-- datapath sigs
		zc0 : in std_logic;
		zc256 : in std_logic; 
		ein : out std_logic;
		lc : out std_logic;
		ec : out std_logic;
		
		-- Control communication
		block_read 	: in std_logic;	
		block_ready_set : out std_logic;
		msg_end_set : out std_logic;
		
		-- FIFO communication
		src_ready : in std_logic;
		src_read    : out std_logic	
		);
	end component;	 
	
	component fsm2 is 
		port (
			-- global
			clk : in std_logic;
			rst : in std_logic;
			
			-- datapath
			er : out std_logic;
			si : out std_logic;		
			sf : out std_logic;
			lo : out std_logic;		
			
			-- control				   
				--fsm1 hand shake signals
			block_ready_clr : out std_logic;		
			msg_end_clr 	: out std_logic;
			block_read		: out std_logic;
			
			block_ready		: in std_logic;
			msg_end 		: in std_logic;	
					
				--fsm3 handshake signals
			output_write_set : out std_logic;
			output_busy_set  : out std_logic;
			output_busy		 : in  std_logic
		);							   
	end component; 
	
	component fsm3 is					
		port (	   
			--global
			io_clk  : in std_logic;
			rst		: in std_logic;
		
			-- datapath
			eo : out std_logic;
			
			-- fsm 2 handshake signal
			output_write : in std_logic;	
			output_write_clr : out std_logic;	
			output_busy_clr  : out std_logic;	
			
			-- fifo
			dst_ready : in std_logic;
			dst_write : out std_logic
		);
	end component;	   
	
	component datapath is					
		port (
			--external
			clk : in std_logic;
			io_clk: in std_logic;	  		
			din : in std_logic_vector(63 downto 0);
			dout : out std_logic_vector(63 downto 0);
			--FSM1
			ein : in std_logic; 
			lc : in std_logic;
			ec : in std_logic;			
			zc256 : out std_logic; 
			zc0 : out std_logic;
			
			-- FSM2			
			er : in std_logic; 
			lo : in std_logic;
			si : in std_logic;
			sf : in std_logic;
			-- FSM3
			eo : in std_logic;
			--top fsm
			last_fast_clock_cycle : in std_logic			
		);
	end component;	 
	
	component top_fsm is
	generic ( 
		log2_fast_to_slow_ratio : integer := 1
	);
	port (				
		-- global
		rst			: in std_logic;
		clk			: in std_logic;
		io_clk 		: in std_logic;
		-- fifo signals
		src_ready	: in std_logic;
		src_read	: out std_logic;
		dst_ready 	: in std_logic;
		dst_write	: out std_logic;
		
		-- datapath signals
			--fsm1
		ec			: out std_logic;
		lc			: out std_logic;
		ein			: out std_logic;		
		zc0			: in std_logic;
		zc256		: in std_logic;
		
			--fsm2
		er			: out std_logic;
		si			: out std_logic;
		sf   		: out std_logic;
		lo			: out std_logic;
		
			-- FSM3
		eo 			: out std_logic;
			--top fsm
		last_fast_clock_cycle : out std_logic			
	);				 
	end component;	  
	
	component sync_clock is
		generic (
		  log2_fast_to_slow_ratio : integer := 1
		);
		port (						 
			rst		   	: in std_logic;
			fast_clock 	: in std_logic;
			slow_clock 	: in std_logic;
			sync		: out std_logic
		);
	end component;
end pack;