library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.pack.all;

entity sync_clock is
	generic (
	  log2_fast_to_slow_ratio : integer := 1
	);
	port (						 
		rst		   	: in std_logic;
		fast_clock 	: in std_logic;
		slow_clock 	: in std_logic;
		sync		: out std_logic
	);
end sync_clock;

architecture struct of sync_clock is 	
	signal counter, start : std_logic_vector(log2_fast_to_slow_ratio-1 downto 0);  
	signal zeros : std_logic_vector(log2_fast_to_slow_ratio-1 downto 0) := (others => '0');	  
begin	   			
	count_gen : countern generic map ( N => 1 ) port map ( clk => fast_clock, load => rst, en => '1', input => zeros, output => counter );
	
	start_gen : process( slow_clock )
	begin
		if rising_edge(slow_clock) then
			if ( rst = '1' ) then
				start <= (others => '0');
			else
				start <= counter;	
			end if;
		end if;
	end process;  								
	
	sync <= '1' when ( start = counter and rst = '0') else '0';
end struct;