library ieee;
use ieee.std_logic_1164.all;
use work.pack.all;

entity top is		
	generic (
	   log2_fast_to_slow_ratio : integer := 1 
	); 
	port (		
		-- global
		rst 	: in std_logic;
		clk 	: in std_logic;
		io_clk 	: in std_logic;
		
		--fifo
		src_ready : in std_logic;
		src_read  : out std_logic;
		dst_ready : in std_logic;
		dst_write : out std_logic;		
		din		: in std_logic_vector(63 downto 0);
		dout	: out std_logic_vector(63 downto 0)
	);	   
end top;


architecture struct of top is 
	-- fsm1
	signal ein, lc, ec, zc0, zc256 : std_logic;
	-- fsm2
	signal er, si, sf, lo : std_logic;
	-- fsm3
	signal eo : std_logic;
	-- top fsm
	signal last_fast_clock_cycle : std_logic;
		
begin
	fsm_gen : top_fsm 
		generic map ( log2_fast_to_slow_ratio => log2_fast_to_slow_ratio )
		port map (
		rst => rst, clk => clk, io_clk => io_clk,
		src_ready => src_ready, src_read => src_read, dst_ready => dst_ready, dst_write => dst_write,	  
		ec => ec, lc => lc, ein => ein, zc0 => zc0, zc256 => zc256,
		er => er, lo => lo, si => si, sf => sf,
		eo => eo,			   
		last_fast_clock_cycle => last_fast_clock_cycle
	);			
	
	datapath_gen : datapath port map (
		clk => clk, io_clk => io_clk, din => din, dout => dout,
		ein => ein, lc => lc, ec => ec, zc0 => zc0, zc256 => zc256,
		er => er, lo => lo, si => si, sf => sf,
		eo => eo,
		last_fast_clock_cycle => last_fast_clock_cycle
	);

end struct;