library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.pack.all;

entity top_fsm is		
	generic ( 
		log2_fast_to_slow_ratio : integer := 1
	);
	port (					
		rst			: in std_logic;
		clk			: in std_logic;
		io_clk 		: in std_logic;
		
		-- datapath signals
			--fsm1
		ec			: out std_logic;
		lc			: out std_logic;
		ein			: out std_logic;		
		zc0			: in std_logic;
		zc256		: in std_logic;
		
			--fsm2
		er			: out std_logic;
		si			: out std_logic;
		sf   		: out std_logic;
		lo			: out std_logic;
		
			-- FSM3
		eo 			: out std_logic;
			--top fsm
		last_fast_clock_cycle : out std_logic;				
		
		-- fifo signals
		src_ready	: in std_logic;
		src_read	: out std_logic;
		dst_ready 	: in std_logic;
		dst_write	: out std_logic
	);				 
end top_fsm;

architecture struct of top_fsm is				   	 
	-- fsm1
	signal block_ready_set, msg_end_set : std_logic;
	
	-- fsm2						
		-- fsm1 communications
	signal block_ready_clr, msg_end_clr : std_logic; --out
	signal block_ready, msg_end : std_logic; --in
	signal block_read : std_logic;  --in to fsm1
		-- fsm2 communications
	signal output_write_set, output_busy_set : std_logic; --out
	signal output_busy : std_logic; --in 
	
	-- fsm3										
	signal output_write : std_logic; -- in
	signal output_write_clr, output_busy_clr : std_logic; --out	   
	
	-- sync sigs
	signal last_fast_clock_cycle_s : std_logic;
	signal block_ready_clr_sync, msg_end_clr_sync : std_logic;
	signal output_write_set_sync, output_busy_set_sync : std_logic;
begin
	
	fsm1_gen : fsm1 port map (
		io_clk => io_clk, rst => rst, 
		zc0 => zc0, zc256 => zc256, ein => ein, lc => lc, ec => ec, 
		block_read => block_read, block_ready_set => block_ready_set, msg_end_set => msg_end_set,
		src_ready => src_ready, src_read => src_read
	);	 
	
	fsm2_gen : fsm2 port map (
		clk => clk, rst => rst, 
		er => er, si => si, sf => sf, lo => lo, 
		block_ready_clr => block_ready_clr, msg_end_clr => msg_end_clr, block_read => block_read, block_ready => block_ready, msg_end => msg_end,
		output_write_set => output_write_set, output_busy_set => output_busy_set, output_busy => output_busy
	); 
	
	fsm3_gen : fsm3 port map (
		io_clk => io_clk, rst => rst, 
		eo => eo, 
		output_write => output_write, output_write_clr => output_write_clr, output_busy_clr => output_busy_clr,
		dst_ready => dst_ready, dst_write => dst_write
	);	 
	
	sync_gen : sync_clock generic map ( log2_fast_to_slow_ratio => log2_fast_to_slow_ratio ) port map ( rst => rst, slow_clock => clk, fast_clock => io_clk, sync => last_fast_clock_cycle_s );	
	
	block_ready_clr_sync 	<= block_ready_clr and last_fast_clock_cycle_s;	 
	msg_end_clr_sync 		<= msg_end_clr and last_fast_clock_cycle_s;
	output_write_set_sync 	<= output_write_set and last_fast_clock_cycle_s;
	output_busy_set_sync 	<= output_busy_set and last_fast_clock_cycle_s;	
	last_fast_clock_cycle <= last_fast_clock_cycle_s;
	
	sr_blk_ready : sr_reg 
	port map ( rst => rst, clk => io_clk, set => block_ready_set, clr => block_ready_clr_sync, output => block_ready);
	
	sr_msg_end : sr_reg 
	port map ( rst => rst, clk => io_clk, set => msg_end_set, clr => msg_end_clr_sync, output => msg_end);
	
	sr_output_write : sr_reg 
	port map ( rst => rst, clk => io_clk, set => output_write_set_sync, clr => output_write_clr, output => output_write );
	
	sr_output_busy : sr_reg  
	port map ( rst => rst, clk => io_clk, set => output_busy_set_sync, clr => output_busy_clr, output => output_busy );
																																		 
end struct;