at the beginning of the class

throughput to area ratio.

Analyze the revised circuit from the point of view of

a. timing

b. area,

by deriving formulae for the following quantities:

A. Timing

a. execution time for a message composed of a single message block (as a function of the clock period, T

b. execution time for a message composed of N message blocks (as a function of the clock period, T

c. time between fully processing two consecutive message blocks (as a function of the clock period, T

d. input throughput for hashing a single long message (= message block size in bits/ delay between loading two consecutive message blocks)

e. the minimum input word size (w<= 64) and the minimum ratio of the input clock frequency to the internal clock frequency (>= 1) for which loading a block of input data takes the same or smaller amount of time than the time necessary to process one block of data

Assume that

- each message block, other than the first block, can be loaded in parallel with processing of the previous message block
- message can be loaded to a message register in words of the size of maximum 64 bits
- the input/output word size, denoted by w in the specification of the hash function interface is independent from the word size used in the specification of your hash function (e.g., message can be loaded/unloaded in words of w=64 bits, and then processed in words of 32-bits)
- clock used to load input message words can have a frequency which is a multiple of the clock frequency used to process data (e.g., the input/output clock frequency can be 4 times higher than the internal clock frequency used to process data.

Express the minimum clock period first as a

e1. sum of delays through major functional blocks (plus the delay and the setup time of a flip-flop)

and then as a

e2. sum of delays of the smallest indivisible components, such as 2-to-1 MUX, 4-to-1 MUX, AND2, XOR3, Full Adder, ROM, RAM (please provide memory size in parentheses), flip-flop, etc. Include the setup time of a flip-flop in your formula. Assume that all adders are implemented as ripple carry adders composed of Full Adders.

B. area

Express the area of your circuit first as a

B1. sum of areas of major functional blocks. Please clearly specify the number of functional blocks of each type.

and then as a

B2. sum of areas of the smallest indivisible components, such as 2-to-1 MUX, 4-to-1 MUX, AND2, XOR3, Full Adder, ROM, RAM (please provide memory size in parentheses), flip-flop, etc. Assume that all adders are implemented as ripple carry adders composed of Full Adders.

2. report with all timing and area formulae (submitted in class and using Blackboard)