Project - Phase 3

due Wednesday, November 11, 7:20pm

at the beginning of the class


Tasks

Revise and optimize your block diagram developed in Phase 2, in such a way that your circuit is optimized for the maximum
throughput to area ratio.

Analyze the revised circuit from the point of view of
  a. timing
  b. area,
by deriving formulae for the following quantities:

A. Timing

a. execution time for a message composed of a single message block (as a function of the clock period, TCLK)

b. execution time for a message composed of N message blocks (as a function of the clock period, TCLK, and the number of message blocks, N)

c. time between fully processing two consecutive message blocks (as a function of the clock period, TCLK)

d. input throughput for hashing a single long message (= message block size in bits/ delay between loading two consecutive message blocks)

e. the minimum input word size (w<= 64) and the minimum ratio of the input clock frequency to the internal clock frequency (>= 1) for which loading a block of input data takes the same or smaller amount of time than the time necessary to process one block of data

Assume that
e. minimum clock period

Express the minimum clock period first as a
e1. sum of delays through major functional blocks (plus the delay and the setup time of a flip-flop)
and then as a
e2. sum of delays of the smallest indivisible components, such as 2-to-1 MUX, 4-to-1 MUX, AND2, XOR3, Full Adder, ROM, RAM (please provide memory size in parentheses), flip-flop, etc. Include the setup time of a flip-flop in your formula. Assume that all adders are implemented as ripple carry adders composed of Full Adders.

B. area

Express the area of your circuit first as a
B1. sum of areas of major functional blocks. Please clearly specify the number of functional blocks of each type.
and then as a
B2. sum of areas of the smallest indivisible components, such as 2-to-1 MUX, 4-to-1 MUX, AND2, XOR3, Full Adder, ROM, RAM (please provide memory size in parentheses), flip-flop, etc. Assume that all adders are implemented as ripple carry adders composed of Full Adders.


Deliverables

1. revised block diagram (submitted in class)

2. report with all timing and area formulae (submitted in class and using Blackboard)