Time and location:
Monday, 4:30-7:10 PM, Engineering Building, room 1109
Monday, 7:30-8:30 PM; Wednesday 6:00-7:00 PM
The Engineering Building, room 3225
Monday, 7:30-9:30 PM; Tuesday 3:00-5:00 PM
Engineering Building, room 3224
submit all your homework and
project reports using Blackboard by
going to http://courses.gmu.edu
Introduces the design of
systems using hardware description languages. Teaches design
methodologies which partition a system into a datapath and controller.
Focuses on synthesizable RTL VHDL code for digital circuit design using
dataflow, structural, and behavioral coding styles. Introduces VHDL
simulation and verification, and FPGA synthesis, placement, routing,
timing analysis and performance optimization. Requires semester-long
project devoted to the design of a complex digital system implemented
Standing. No official course prerequisite is required, but an
undergraduate background in digital logic design is strongly
P. Chu, RTL
Hardware Design Using VHDL: Coding for Efficiency, Portability, and
Wiley-IEEE Press, 2006.
Hubert Kaeslin, Digital
Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication,
Cambridge University Press; 1st Edition, 2008.
Stephen Brown and Zvonko
of Digital Logic with VHDL Design,
3rd Edition, McGraw-Hill, 2008.
Volnei A. Pedroni,
Circuit Design with VHDL,
MIT Press, 2004.
Sundar Rajan, Essential
RTL Synthesis Done Right,
S & G Publishing, 1998.
J. Ashenden, The
Designer's Guide to VHDL,
Edition, Morgan Kaufmann Publishers, 2008.
Software Packages Used in This Class
- Aldec Active HDL
- Mentor Graphics ModelSim
- ModelSim Xilinx Edition III
- Synplicity Synplify Pro
- Xilinx XST
- Xilinx ISE
- Xilinx WebPACK
- Altera Quartus II
- GMU ATHENa
software will be
available in the Computer Engineering Lab, The Engineering Building,
Selected software can be installed on your laptops and home
This year's project will
implementing a selected cryptographic hash function competing in the
contest for a new American hash standard SHA-3.
Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs,
The list and specification of remaining SHA-3 candidates is available here.
Each student will design, implement, and optimize one algorithm assign
to him/her by the instructor. All implementations will be optimized
using multiple criteria and implemented using multiple families of
FPGAs from Xilinx and Altera. This project will support NIST in
selection of a hash algorithm most suitable from the point of view of
by Ekawat Homsirikamol, Marcin Rogawski, and Kris Gaj, Cryptology
ePrint Archive: Report 2010/445 - Revised
October 10, 2010
Second Round 2 SHA-3 Candidates
SHA-3 Zoo - Hardware
Materials from the SHA-3 Project
Review Meeting with NIST on November 9, 2010: - NEW!!!
GMU SHA Core
Interface and Hash Function Performance Metrics [PPT,
PDF2] - NEW!!!
Project Phase 2
Sunday, November 21, 11:59 PM
Project Phase 3
Wednesday, December 1,
mini-SHA example - NEW!!!
Deliverables - due Thursday,
- due Thursday, October 7, 11:59 PM
+ test vectors
+ slides [PPT, PDF]
due Saturday, October 23, 11:59 PM
- due Sunday, November 7, 11:59 PM
be posted gradually here, at least 6 days before a given assignment's
Lecture 1 - Digital Logic Review [PPT, PDF, PDF6]
Lecture 2 - Introduction to
Course Project [PDF, PDF6]
- Introduction to VHDL for Synthesis [PPT,
- Simple Testbenches [PPT, PDF, PDF6]
- Dataflow Modeling of Combinational Logic [PPT, PDF,
- Behavioral Modeling of Sequential-Circuit Building Blocks [PPT,
on Tuesday, Oct. 5 (slides 33, 36, 43, 45)
- Modeling of Circuits with a Regular Structure. Aliases, Attributes,
Packages. Mixing Design Styles. [PPT, PDF,
- RTL Design Methodology. Transition from Pseudocode & Interface
to a Corresponding Block Diagram. [PPT, PDF, PDF2]
- FPGA Devices & FPGA Device Flow.
- Advanced Testbenches.
[PPT, PDF, PDF6]
- ATHENa & FPGA Embedded Resources.
PDF6] - revised on Monday, Nov. 22, 8:00pm
(slides 29, 44, 65)
- Design of Controllers. Finite State Machines and Algorithmic State
Machine (ASM) Charts.
will be posted gradually
here, at least one day before a given
Instructions: Templates & Examples
Asked Questions about VHDL from comp.lang.vhdl - NEW!!!
HDL Modeling Guidelines
Carb VHDL Tutorial - by Bryan
vhdl.org - HDL Resources
of EDA Industry Working Groups - NEW!!!
Past Course Web
(with Dr. Hwang) Fall
(with Dr. Gaj)
(with Dr. Gaj)
and Past Exams