due Thursday, October 7, 11:59 pm
submission using Blackboard
a. Describe a circuit shown in the diagram below using dataflow design style of
i.e., using concurrent statements only.
Please note that the nodes with the same name are
For the priority encoder, w3 is an input with the highest
priority, and z is active when at least one input is active. All inputs
and outputs are active high.
b. Write a testbench capable of
verifying the operation of this circuit for all possible combinations
of inputs (a, b, c, d).
c. Simulate your circuit and verify its functionality by verifying
output(s) of each individual component included in the circuit over the
entire duration of the simulation.
d. Based on the simulation, determine the truth table of the function
y=f(a, b, c, d) implemented by this circuit.
e. Propose at least one alternative implementation of the same
function, for example, using a circuit composed of a tri-state buffer
f. Describe your alternative circuit in VHDL and verify its
functionality using simulation based on the same testbench.
- logic gates only
- multiplexers only
- ROM only.
What to Turn In:
Submit the following files using Blackboard. Please DO NOT
your entire Aldec Active-HDL project directory with all its files,
subdirectories, temp files, etc.; submit only what is requested
- Two synthesizable source code files (for the basic circuit and
for your alternative circuit)
- Waveforms from the simulation of both circuits using Aldec