Homework 3

due Sunday, November 7, 11:59 pm

submission using Blackboard


Problems

a. Go over the two tutorials posted at the course web page
Use example recommended in these tutorials.

b. Modify your solution to Homework 1, by adding registers at the input and output of your circuit.
    Adjust your testbench accordingly.

c. Synthesize and Implement your solution to Homework 1 using FPGA Design Flow based on Aldec Active-HDL.

d. Synthesize and Implement your solution to Homework 2 using FPGA Design Flow based on Xilinx ISE Webpack and ModelSim.

In both cases, repeat your experiment for the smallest device of the following two families capable of holding the circuit:
Use the fastest speed grade available to you.

As a part of your design flow for points c. and d. perform the following tasks:

1. Synthesize your circuit using Xilinx XST.  Do your best to remove any potential errors and at least majority of warnings. Analyze the contents of the report files.

2. Perform post-synthesis simulation of your circuit and make sure that this simulation returns exactly the same results as functional simulation.

3. Implement your circuit using Xilinx tools. Do your best to remove any potential errors and at least majority of warnings. Analyze the contents of of the report files.

4. Perform timing simulation of your circuit and make sure that this simulation returns the same logical values, as functional simulation, for a clock frequency close to the maximum clock frequency of the analyzed circuit after placing & routing.

5. Perform static timing analysis and determine the most critical path in your circuit. Mark this path in the respective block diagram.

6. Optimize your circuit for maximum clock frequency using options of tools and/or changes in your VHDL code.

7. Report the following data after optimization:

What to Turn In:

Submit the following files using Blackboard. DO NOT submit your entire Aldec or Xilinx project with all its files, directories, subdirectories, temp files, etc.; only submit what is requested below.