due Sunday, November 7, 11:59 pm
submission using Blackboard
a. Go over the two tutorials posted at the course web page
Use example recommended in these tutorials.
b. Modify your solution to Homework 1, by adding registers at the input
and output of your circuit.
Adjust your testbench accordingly.
c. Synthesize and Implement your solution to Homework 1 using FPGA
Design Flow based on Aldec Active-HDL.
d. Synthesize and Implement your solution to Homework 2 using FPGA
Design Flow based on Xilinx ISE Webpack and ModelSim.
In both cases, repeat your experiment for the smallest device
of the following two families capable of holding the circuit:
Use the fastest speed grade available to you.
As a part of your design flow for points c. and d. perform the
1. Synthesize your circuit using Xilinx XST. Do your best to
remove any potential
errors and at least majority of warnings. Analyze the contents
of the report files.
2. Perform post-synthesis simulation of your circuit and make sure that
this simulation returns exactly the same results as functional
3. Implement your circuit using Xilinx tools. Do your best to remove
any potential errors and at least majority of warnings. Analyze the
contents of of the report files.
4. Perform timing simulation of your circuit and make sure that
this simulation returns the same logical values, as functional
simulation, for a clock frequency close to the maximum clock frequency
of the analyzed circuit after placing &
5. Perform static timing analysis and determine the most critical path
in your circuit. Mark this path in the respective block diagram.
6. Optimize your circuit for maximum clock frequency using options of
tools and/or changes in your VHDL code.
7. Report the following data after optimization:
- FPGA device used
- minimum clock period after synthesis
- maximum clock frequency after synthesis
- minimum clock period after placing & routing
- maximum clock frequency after placing & routing
- number of CLB slices
- number of LUTs
- number of flip-flops
- number of Block RAMs
- number of DSPs
- number of I/O blocks
- all non-default options of tools
- logic components included in the critical path.
What to Turn In:
Submit the following files using Blackboard. DO NOT submit
your entire Aldec or Xilinx project with all its files, directories,
subdirectories, temp files, etc.; only submit what is requested below.
- All synthesizable source codes (before and after optimization for
- Create a text file called hw3_results.txt. In this text
file, give a short summary including:
- A. FPGA device name and speed grade
- B. Results after synthesis: #slices, #flip-flops, #LUTs,
#BRAMs, #DSPs, #IOs, maximum clock frequency, minimum period. If your
only gives slices instead of LUTs (or vice-versa) after synthesis, just
note this in your text file.
- C. Results after implementation: #slices, #flip-flops, #LUTs,
#BRAMs, #DSPs, #IOs, maximum clock frequency, minimum period
- D. logic components included in the critical path.
- E. your explanation of differences between the amount of
resources used in Spartan 3 and Virtex 5.
- F. your explanation of differences between the maximum clock
frequencies achievable using Spartan 3 and Virtex 5.
- G. summary of changes introduced to your code in order to
remove synthesis or implementation errors or warnings.
- H. non-default options of tools and/or summary of changes
introduced to your code in order to increase maximum clock frequency
- Synthesis report
- Netlist rtl schematic
- Full implementation report(s)
- Static timing analysis report
- Waveforms from simulation before synthesis (in .awf format for
Active HDL or .wlf format for ModelSim)
- Waveforms from simulation post-synthesis (in .awf format for
Active HDL) or post-translate (in .wlf format for ModelSim)
- Waveforms from timing simulation post place-and-route (in .awf
format for Active HDL or .wlf format for ModelSim)