Project - Phase 2

due Sunday, November 21th, 11:59 pm

submission using Blackboard

Problems

a. Analyze carefully the source code of the basic architecture of your hash function provided to you by the instructor.
    For the datapath of the circuit, compare the RTL source code vs. block diagrams published in the ePrint paper.
    Clearly mark on the diagrams any discrepencies you have identified.

b. Verify the correctness of the source codes using testbenches provided with the code, especially the testbench for the top level circuit.

c. Synthesize the code with default options of tools, except the options that prohibit the use of DSP units and Block RAMs, which should be turned on if embedded resources are inferred by    default options of the synthesis tools. Analyze the obtained synthesis reports. Verify the obtained netlist through post-synthesis simulation.

d. Implement the code with default options of tools, except the options that prohibit the use of DSP units and Block RAMs, which should be turned on if embedded resources are inferred by default options of tools. Analyze the obtained implementation reports. Verify the obtained post-place-and-route netlist through timing simulation.

In both cases, repeat your experiment for the best matching device of the following two families capable of holding the circuit:
Use the fastest speed grade available to you.

You can use either the FPGA Design Flow based on Aldec Active-HDL or FPGA Design Flow based on Xilinx ISE Webpack and ModelSim, per your personal preference.

e. Rewrite the source code of the datapath portion of the circuit, so it matches your diagram for a selected folded architecture. If you can cover multiple folding factors, using the same code, with different values of generics, you should attempt to do so.

f. Draw interfaces between the datapath and the control portion of the circuit for the basic architecture, and for the selected folded architecture(s).
    Identify differences between these two interfaces.

g. Do your best to verify the operation of your new datapath source codes, for example by providing correct sequence of control signals directly from the testbench, rather than from the control unit. Use any testbenches developed for the basic architecture, as well as the C reference code for your SHA-3 candidate, as sources of test vectors.

What to Turn In:

Submit the following files using Blackboard. DO NOT submit your entire Aldec or Xilinx project with all its files, directories, subdirectories, temp files, etc.; only submit what is requested below.

Re: a. Marked up and scanned block diagrams.
Re: b. Report on tests you have run for functional simulation, and results of these tests.
Re: c. Your own summary of post-synthesis results: #slices, #flip-flops, #LUTs, #BRAMs, #DSPs, #IOs, maximum clock frequency, minimum period.
          Report on tests you have run for post-synthesis simulation, and results of these tests. Full text of the post-synthesis report.
Re: d. Your own summary of post-implementation results: #slices, #flip-flops, #LUTs, #BRAMs, #DSPs, #IOs, maximum clock frequency, minimum period.
          Report on tests you have run for timing simulation, and results of these tests. Full texts of the implementation reports.
Re: e. RTL source code of the datapath of your selected folded architecture(s)
Re: f. Diagrams of the interfaces, for the basic architecture, and for your selected folded architecture(s).
Re: g. Source code of the testbench. Test vectors used. Report on results of the verification.