Project - Phase 3

due Wednesday, December 1st, 11:59 pm

submission using Blackboard

Tasks

Perform the given below Design Tasks and Benchmarking Tasks in parallel to each other:

Design Tasks

a. Select at least three architectures you would like to fully implement as a part of the Project (Exceptions: students working on SIMD and BMW are expected to implement at least two architectures).

These architectures should include:
Your list may include for example:
Send your selection to the instructor by e-mail for a final approval.

b. draw a modified block diagram of your embedded-resource-based architecture. Use xfig. Submit both .fig and .pdf files.
    Exceptions: This task is not required for BMW, CubeHash, Luffa, and Skein.

For the AES-based hash algorithms, you can use either
per your preference.

c. develop generic VHDL codes for all
used by your hash function.

Your code should allow choosing between implementations based on
using generics, separate for each resource type.

Your code should generate expected results in terms of resource utilization after synthesis and implementation for at least the following families:
Verify this behavior using ATHENa.
Please note that Cyclone II and Cyclone IV do not contain distributed LE-based memory.
Please develop at least codes based on instantiation (manual or supported by Xilinx CORE Generator and/or Altera MegaWizard Plug-In Manager).
The codes based on inference can be submitted for bonus points.
Benchmarking Tasks

a. Upgrade your installation of Xilinx ISE to version 12.3 (optional)

b. Perform the one-time tasks necessary to start working with ATHENa
c. Run ATHENa for the default example, sha256_rs
Review carefully:
d. Run ATHENa for a different example: test_circuit
Review carefully the corresponding:
e. Run ATHENa for the basic architecture of your hash function using
Make sure to prevent the use of embedded FPGA resources, by setting (in design.config.txt):
        MAX_BRAM_UTILIZATION = 0 (Xilinx devices only)
        MAX_MEMORY_UTILIZATION = 0 (Stratix III and Stratix IV only)
        MAX_MUL_UTILIZATION = 0 (Spartan 3 only)
        MAX_DSP_UTILIZATION = 0.

Try different ATHENa applications, such as
Feel free to change the contents of the corresponding configuration files specific to each of these ATHENa applications.
Tabulate the best obtained results and the corresponding execution time for each application.
The number of applications and their parameters you will be able to test will depend on the complexity of your circuit.
For the most complex hash functions (SIMD, ECHO, BMW), single_run will be sufficient.

f. extract the best obtained results in terms of
for each of the evaluated families, using db_report_generator.


What to Turn In:

Submit the following files using Blackboard

Design Tasks

Re: a) a list of selected architectures (also to be sent by e-mail before the Phase 3 deadline)
Re: b) block diagram of the embedded-resource-based architecture (.fig and .pdf files)
Re: c) generic VHDL codes of implemented components + reports from ATHENa confirming that your codes generate reports with the expected utilization of embedded resources.

Benchmarking Tasks

Re: c) report_summary.txt for sha256_rs and/or report on any encountered problems
Re: d) report_summary.txt for test_circuit and/or report on any encountered problems
Re: e) multiple sets: {modified configuration files, report_summary.txt} corresponding to your experiments. Table with the best obtained results and the corresponding execution time for each application. Report on any encountered problems.
Re: f) CSV files generated by db_report_generator.

Re: all) Short report summarizing your experiences with ATHENa so far:  negative: bugs, difficulties, etc.; positive: most useful features; wish list: most useful extensions.