ECE 545
Digital System Design with VHDL

Fall 2011


Time and location:    Thursday, 4:30-7:10 PM, Art and Design Building, room L008

Instructor:                 Kris Gaj  
Email:                         kgaj@gmu.edu
Office hours:            Tuesday 6:00-7:00PM, Thursday 7:30-8:30 PM, and by appointment
                                    The Engineering Building, room 3225

TA:                              Umar Sharif
Office hours:
           Tuesday 6:00-7:00PM, Thursday 7:30-8:30 PM, and by appointment
                                    The Engineering Building, room 3231
Email: 
                       
msharif2@masonlive.gmu.edu



Please submit all your homework and project reports using MyMason by going to http://mymason.gmu.edu


Course Description

Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis and performance optimization. Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs. 

Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly recommended.


Required Textbooks

Pong P. ChuRTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006.

 

Supplementary Textbooks

Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Edition, McGraw-Hill, 2008.

Volnei A. Pedroni, Circuit Design and Simulation with VHDL, 2nd Edition, The MIT Press, 2010.

Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998.

Peter J. Ashenden, The Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann Publishers, 2008.
 

Software Packages Used in This Class

All software will be available in the Computer Engineering Labs, The Engineering Building, rooms 3208 and 3204.
Selected FREE software can be installed on your laptops and home workstations.

Course Outline (subject to possible modifications):

  1. Digital Logic Review.   09/01/2011
  2. SHA-3 Competition. Introduction to the Course Project.  09/08/2011
  3. RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram.  09/15/2011
  4. Introduction to VHDL for Synthesis. Simple Testbenches.  09/22/2011
  5. Dataflow Modeling of Combinational Logic.  09/29/2011
  6. Behavioral Modeling of Sequential-Circuit Building Blocks. Mixing Design Styles.  10/06/2011
  7. FPGA Devices & FPGA Device Flow.   10/13/2011
  8. Modeling of Circuits with Regular Structure. Functions and Procedures.  10/20/2011
  9. Midterm Exam.  10/27/2011
  10. Midterm Exam - Review. Design of Controllers. Finite State Machines.  11/03/2011
  11. Algorithmic State Machine (ASM) Charts.  11/10/2011
  12. Design of Controllers Using ASM Charts - Examples. Advanced Testbenches.  11/17/2011
  13. Modern FPGA Devices. ATHENa - Automated Tool for Hardware EvaluatioN.   12/01/2011
  14. FPGA Embedded Resources. Modeling of Memories in FPGAs. Project Deliverables. 12/08/2011

Project Tasks

This year's project will involve implementing a selected cryptographic hash function competing in the contest for a new American hash standard SHA-3.
The list and specification of remaining SHA-3 candidates is available here. Each student will design, implement, and optimize one algorithm assign to him/her by the instructor. All implementations will be optimized using multiple criteria and implemented using multiple families of FPGAs from Xilinx and Altera. This project will support NIST in selection of a hash algorithm most suitable from the point of view of  hardware efficiency.

Project Tasks due Thursday, October 20, 2011

Project Resources

Round 3 SHA-3 Candidates

GMU Source Codes and Block Diagrams of Round 3 SHA-3 Candidates

ATHENa Database of Results

SHA-3 Zoo - Hardware Implementations

Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs,
by Ekawat Homsirikamol, Marcin Rogawski, and Kris Gaj, Cryptology ePrint Archive: Report 2010/445 - Revised December 21, 2010

ATHENa Website

FPGA Embedded Resources



Homework

Solutions to Homework 4 - posted December 31, 2011

Homework 4 - due Saturday, December 3, 2011, 11:59pm (submission using MyMason)


Homework 3 - due Monday, October 31, 2011, 11:59pm (submission using MyMason)


Homework 2 - due Sunday, October 16, 2011, 11:59pm (submission using MyMason)

Homework 1 - revised solution for Problem 2, drawn using Xfig, due on Monday, October 3, 11:59pm (the Xfig file and the corresponding PDF file must be submitted using MyMason)

Homework 1 - Problems 1 & 3, due on Thursday, September 22, 4:30pm (graded for bonus points only)

Homework assignments will be posted gradually here, at least 6 days before a given assignment's due date.

 

Viewgraphs

Follow-up Courses [PPT, PDF]

Master's Thesis Presentation on Padding Units by Ambarish Vyas [PDF]

Project Deliverables. [PPT, PDF]

Lecture 12 - FPGA Embedded Resources. [PPT, PDF, PDF6]

Lecture 11 - Modern FPGA Devices. ATHENa - Automated Tool for Hardware EvaluatioN. [PPT, PDF, PDF6]

Lecture 10 - Design of Controllers. Finite State Machines and Algorithmic State Machine (ASM) Charts. [PPT, PDF, PDF6]

Lecture 9 - Modeling of Circuits with a Regular Structure. Aliases, Attributes, Packages. [PPT, PDF, PDF6]

Lecture 8 - FPGA Devices & FPGA Device Flow. [PPT, PDF, PDF6]

Lecture 7 - Advanced Testbenches. [PPT, PDF, PDF6]

Lecture 6 - Behavioral Modeling of Sequential-Circuit Building Blocks. Mixing Design Styles. [PPT, PDF, PDF6]

Lecture 5 - Dataflow Modeling of Combinational Logic. [PPT, PDF, PDF6]

Lecture 4 - Introduction to VHDL for Synthesis. Simple Testbenches. [PPT, PDF, PDF6]

Lecture 3 - RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram. [PPT, PDF, PDF6]

Lecture 2 - Course Organization. Introduction to the Course Project. [PPT, PDF, PDF6]

Lecture 1 - Digital Logic Review [PPT, PDF, PDF6]

Viewgraphs will be posted gradually here, at least one day before a given lecture.

 

Reference Material

VHDL

VHDL Instructions: Templates & Examples

Frequently Asked Questions about VHDL from comp.lang.vhdl

OpenCores HDL Modeling Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy

vhdl.org - HDL Resources of EDA Industry Working Groups

 

Tools

The Detailed Instructions on How to Configure your FPGA Tools at School, and Install and Configure your FPGA Tools at Home (last updated 09/25/2011)

Aldec Tools - Installation Guide (last updated 10/13/2011)


Xfig - Installation and Start-up Guide (last updated 09/25/2010)

Xfig - Export to PDF Format (last updated 12/30/2011)

Tutorial on Simulation using Aldec Active-HDL (last updated 09/25/2011)

Tutorial on FPGA Design Flow based on Aldec Active-HDL (last updated 10/22/2011)

Tutorial on Tutorial on Critical Path Analysis using Synplify Premier DP (last updated 11/18/2011)

Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim (last updated 10/31/2010

Tutorial on Concurrent Version System based on CVS NT and Tortoise CVS


Past Course Web Pages

ECE 545:     Fall 2008 (with Dr. Hwang)   Fall 2009 (with Dr. Gaj)   Fall 2010 (with Dr. Gaj)

ECE 448:     Spring 2011 (with Dr. Gaj)

 

Practice and Past Exams

Final Exam 2011

Solutions to the Final Exam 2011:  all deliverables (zip)

Solutions to the Final Exam 2011 (selected deliverables in PDF): 

  block diagram, interface, ASM chart, short report


Midterm Exam 2011

Solutions to the Midterm Exam 2011:  [PDF, PPT]

Source codes for Task 3:  reg.vhd, ROM_16x4.vhd, main_iterative_loop.vhd

Source Codes for Task 5:  exam_top_tb.vhd

Midterm Exam 2010

Final Exam 2010


Midterm Exam 2009

Solutions to the Midterm Exam 2009: Task 1  Task 2  Task 3  Task 4

Midterm Exam 2009: Recommended Reading and Practice Problems

Final Exam 2009

Midterm Exam 1 from Fall 2006

Midterm Exam 1 from Fall 2005

Midterm Exam 1 from Fall 2004

 

Midterm Exam 2 from Fall 2006

Midterm Exam 2 from Fall 2005

Midterm Exam 2 from Fall 2004