## Homework 3

### Problems

a. Go over the following tutorial posted on the course web page
Use example recommended in this tutorial.

b. Synthesize and implement your solution to Homework 2 using FPGA Design Flow based on Aldec Active-HDL.

Use
• the smallest device of the Spartan 3 family
• the fastest speed grade available to you
• Xilinx XST for synthesis
• default options of tools.

1. Synthesize your circuit using Xilinx XST.  Do your best to remove any potential errors and at least majority of warnings. Document and report all changes you have had to introduce to the source codes. Analyze the contents of the report files.

2. Perform post-synthesis simulation of your circuit, and make sure that this simulation returns exactly the same results as functional simulation.

3. Implement your circuit using Xilinx tools. Do your best to remove any potential errors and at least majority of warnings. Document and report all changes you have had to introduce to the source codes. Analyze the contents of the report files.

4. Perform timing simulation of your circuit, and make sure that this simulation returns the same logical values as functional simulation.
Perform this simulation twice, first with a relatively large clock period, e.g., 100 ns, and then for a clock period close to the minimum clock period of the analyzed circuit after placing & routing (as seen in the implementation reports).

5. Perform static timing analysis and determine the most critical path in your circuit. Mark this path in your block diagram developed as a part of Homework 1.

6. Locate and include in your homework report the following results:
• FPGA device used
• minimum clock period after synthesis
• maximum clock frequency after synthesis
• minimum clock period after placing & routing
• maximum clock frequency after placing & routing
• number of CLB slices
• number of LUTs
• number of flip-flops
• number of Block RAMs
• number of embedded multipliers, MULT18X18s
• number of I/O blocks
• logic components included in the critical path.
8. Estimate analytically the number of Logic Cells used by each component of your block diagram other than multipliers. Calculate the total number of Logic Cells and the total number of CLB slices that should be used by your circuit based on your analysis.
• Compare your estimated values with actual values obtained in Task 6.
• Try to explain the possible discrepencies.
9. Repeat steps 1, 3, 5 and 6 for the following non-default option of tools:
• Multplier style:   LUT.
Determine the number of CLB slices used to implement a single 8x8 bit multiplier mod 256 using reconfigurable logic rather than 18x18-bit embedded multiplier.

Bonus Problem:

Repeat steps 1-6 using Synplify Premier DP. Analyze the critical path of your circuitr using schematic view and the "show critical path" option of Synplify Premier DP.
Compare all results obtained using Xilinx XST with corresponding results obtained using Synplify Premier DP.

What to Turn In:

Submit the following files using Blackboard. DO NOT submit your entire Aldec project with all its files, directories, subdirectories, temp files, etc.
Only submit what is requested below.
• Comprehensive report discussing all outcomes of Tasks 1-9 (and possibly Bonus Problem).
• All synthesizable source codes
• Testbenches
• Synthesis reports
• All implementation report(s)
• Static timing analysis repors
• Waveforms from functional simulation (in .awf format and as a single screenshot proving correct operation)
• Waveforms from post-synthesis simulation (in .awf format and as a single screenshot proving correct operation)
• Waveforms from timing simulation (in .awf format as a single screenshot proving correct operation)
• Block diagram with the marked-up critical path.