due Saturday, December 3, 11:59 pm
submission using Blackboard
Develop a control unit for a circuit EXAM specified in the text of
Assume that the Datapath and the Interface with the Division to the
Datapath and the Controller are given to you in the Solutions
to the Midterm Exam.
Please follow the given below steps of the design process:
- Draw an ASM chart of the Control Unit
- Translate your ASM chart into VHDL
- Develop a testbench for the Control Unit
- Fully debug your VHDL code of the Controller using your
- Develop a full code of the Datapath, using as a basis the code
for the main iterative loop given in Solutions to the Midterm
Exam, under Source Codes for Task 3.
- Write a source code of your top level unit, instantiating your
Datapath and your Controller
- Test your entire circuit using exam_top_tb.vhd
and the following reference C
- Synthesize and implement your solution using
As a part of your design flow perform the following tasks:
- the smallest device of the Spartan 3 family
- the fastest speed grade available to you
- Xilinx XST for synthesis
- default options of tools.
A. Synthesize your circuit using Xilinx XST. Do your best to
remove any potential errors and at least majority of warnings.
B. Perform post-synthesis simulation of your circuit, and make sure
that this simulation returns exactly the same results as functional
C. Implement your circuit using Xilinx tools. Do your best to remove
any potential errors and at least majority of warnings.
D. Perform timing simulation of your circuit, and make sure that
this simulation returns the same logical values as functional
Perform this simulation twice, first with a
relatively large clock period, e.g., 100 ns, and then for a clock
period close to the minimum clock period of the analyzed circuit
after placing & routing (as seen in the implementation reports).
E. Perform static timing analysis and determine the most critical
path in your circuit after implementation. Mark this path in the
block diagram of the Datapath.
F. Locate and include in your homework report the following results:
- FPGA device used
- minimum clock period after synthesis
- maximum clock frequency after synthesis
- minimum clock period after placing & routing
- maximum clock frequency after placing & routing
- number of CLB slices
- number of LUTs
- number of flip-flops
- number of I/O blocks
Bonus Problem 1:
Repeat steps A-F using Synplify Premier DP. Analyze the
critical path of your circuitr using schematic view and the "show critical path"
option of Synplify Premier DP, as described in the Tutorial
on Critical Path Analysis using Synplify Premier DP.
Compare all results obtained using Xilinx XST with corresponding
results obtained using Synplify Premier DP.
Bonus Problem 2:
Determine the amount of FPGA resources and maximum clock
frequency separately for the Datapath and the Controller.
What to Turn In:
Submit the following files using Blackboard. DO NOT
submit your entire Aldec project with all its files, directories,
subdirectories, temp files, etc.
Only submit what is requested below.
- Comprehensive report discussing all outcomes of Tasks 1-8 (and
possibly Bonus Problems).
- ASM chart of the Controller
- All synthesizable source codes, including full source codes
for the Controller, the Datapath, and the Top-Level Circuit
- Testbench for the Controller, and Testbench for the Top-Level
- Synthesis reports
- All implementation report(s)
- Static timing analysis repors
- Waveforms from functional simulation (in .awf format and as a
single screenshot proving correct operation)
- Waveforms from post-synthesis simulation (in .awf format and
as a single screenshot proving correct operation)
- Waveforms from timing simulation (in .awf format as a single
screenshot proving correct operation)
- Block diagram with the marked-up critical path.