Homework 4

due Saturday, December 3, 11:59 pm

submission using Blackboard


Problems

Develop a control unit for a circuit EXAM specified in the text of the Midterm Exam.
Assume that the Datapath and the Interface with the Division to the Datapath and the Controller are given to you in the Solutions to the Midterm Exam.

Please follow the given below steps of the design process:
  1. Draw an ASM chart of the Control Unit

  2. Translate your ASM chart into VHDL

  3. Develop a testbench for the Control Unit

  4. Fully debug your VHDL code of the Controller using your testbench

  5. Develop a full code of the Datapath, using as a basis the code for the main iterative loop given in Solutions to the Midterm Exam, under Source Codes for Task 3.

  6. Write a source code of your top level unit, instantiating your Datapath and your Controller

  7. Test your entire circuit using exam_top_tb.vhd and the following reference C implementation

  8. Synthesize and implement your solution using
As a part of your design flow perform the following tasks:

A. Synthesize your circuit using Xilinx XST.  Do your best to remove any potential errors and at least majority of warnings.

B. Perform post-synthesis simulation of your circuit, and make sure that this simulation returns exactly the same results as functional simulation.

C. Implement your circuit using Xilinx tools. Do your best to remove any potential errors and at least majority of warnings.

D. Perform timing simulation of your circuit, and make sure that this simulation returns the same logical values as functional simulation.
    Perform this simulation twice, first with a relatively large clock period, e.g., 100 ns, and then for a clock period close to the minimum clock period of the analyzed circuit after placing & routing (as seen in the implementation reports).

E. Perform static timing analysis and determine the most critical path in your circuit after implementation. Mark this path in the block diagram of the Datapath.

F. Locate and include in your homework report the following results:

Bonus Problem 1:

Repeat steps A-F using Synplify Premier DP. Analyze the critical path of your circuitr using schematic view and the "show critical path" option of Synplify Premier DP, as described in the Tutorial on Critical Path Analysis using Synplify Premier DP.
Compare all results obtained using Xilinx XST with corresponding results obtained using Synplify Premier DP.

Bonus Problem 2:

Determine the amount of FPGA resources and maximum clock frequency separately for the Datapath and the Controller.

What to Turn In:


Submit the following files using Blackboard. DO NOT submit your entire Aldec project with all its files, directories, subdirectories, temp files, etc.
Only submit what is requested below.