ECE 545
Digital System Design with VHDL

Fall 2012


Time and location:    Thursday, 4:30-7:10 PM, The Nguyen Engineering Building, room 1108

Instructor:                 Kris Gaj  
Email:                         kgaj@gmu.edu
Office hours:            Tuesday 7:30-8:30PM, Thursday 7:30-8:30 PM, and by appointment
                                    The Engineering Building, room 3225

TA:                              Umar Sharif
Office hours:
            Thursday 7:30-8:30 PM, and by appointment
                                     The Engineering Building, room 3231
Email: 
                        
msharif2@masonlive.gmu.edu



Please submit all your homework and project reports using MyMason by going to http://mymason.gmu.edu


Course Description

Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis and performance optimization. Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs. 

Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly recommended.


Required Textbooks

Pong P. ChuRTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006.

 

Supplementary Textbooks

Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Edition, McGraw-Hill, 2008.

Volnei A. Pedroni, Circuit Design and Simulation with VHDL, 2nd Edition, The MIT Press, 2010.

Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998.

Peter J. Ashenden, The Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann Publishers, 2008.
 

Software Packages Used in This Class

All software will be available in the Computer Engineering Labs, The Engineering Building, rooms 3208 and 3204.
Selected FREE software can be installed on your laptops and home workstations.

Course Outline (subject to possible modifications):

  1. Organization of the Course. Introduction to the Course Project.   08/30/2012
  2. Digital Logic Refresher.  09/06/2012
  3. RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram.  09/13/2012
  4. VHDL Basics. Testbenches.  09/20/2012
  5. Dataflow Modeling of Combinational Logic.  09/27/2012
  6. Behavioral Modeling of Sequential-Circuit Building Blocks. Mixing Design Styles.  10/04/2012
  7. FPGA Devices & FPGA Device Flow.   10/11/2012
  8. Timing Analysis. 10/18/2012
  9. Modeling of Circuits with Regular Structure. Functions and Procedures.  10/25/2012
  10. Midterm Exam.  11/01/2012
  11. Hardware Architectures of Secret-Key Block Ciphers and Hash Functions. 11/08/2012
  12. Design of Controllers. Finite State Machines and Algorithmic State Machine (ASM) Charts. 11/15/2012
  13. Design of Controllers - Examples. Alternative Coding Styles. Modeling of Memories in FPGAs 11/29/2012
  14. Project Deliverables. ATHENa - Automated Tool for Hardware EvaluatioN. Modern FPGA Devices. 12/06/2012
  15. Final Exam. 12/13/2012

Project Tasks

This year's project will involve implementing a selected authenticated cipher. Each student will design, implement, and optimize one algorithm assign to him/her by the instructor. All implementations will be optimized using multiple criteria and implemented using multiple families of FPGAs from Xilinx and Altera. This project will support standardization organizations, such as NIST, in selection of a new authenticated encryption standard most suitable from the point of view of hardware efficiency.

Project Resources

Project  Deliverables - due Saturday, December 15, 11:59 PM

ATHENa Website

ATHENa Database of Results

DIAC - Directions in Authenticated Ciphers

GMU Source Codes and Block Diagrams of Round 3 SHA-3 Candidates

FPGA Embedded Resources


Homework

Homework 5 - due Wednesday, October 24, 11:59pm

Homework 4 - due Saturday, October 13, 11:59pm

Homework 3 - due Thursday, October 4, 4:30pm

Homework 2 - due Thursday, September 27, 4:30pm


Homework 1 - due Thursday, September 20, 4:30pm

   Solutions: Block Diagram, Interface with the Division into Datapath & Controller

Homework assignments will be posted gradually here, at least 6 days before a given assignment's due date.

 

Viewgraphs


Lecture 12 - ATHENa - Automated Tool for Hardware EvaluatioN. Modern FPGA Families. [PPT, PDF]

Lecture 11 - Memories in Xilinx FPGAs. [PPT, PDF]

Lecture 10 - Design of Controllers. Finite State Machines and  Algorithmic State Machine (ASM) Charts. (revised 11/29/2012, 11:55PM) [PPT, PDF]

Lecture 9 - Modeling of Circuits with a Regular Structure. Aliases, Attributes, Functions, and Procedures. [PPT, PDF]

Lecture 8b - Hardware Architectures of Secret-Key Block Ciphers and Hash Functions. [PPT, PDF]

Lecture 8a - Timing Analysis. [PPT, PDF]

Lecture 7 - FPGA Design Flow. [PPT, PDF]

Lecture 6 - Behavioral Modeling of Sequential-Circuit Building Blocks. Mixing Design Styles. [PPT, PDF]

Lecture 5 - Dataflow Modeling of Combinational Logic. [PPT, PDF]

Lecture 4 - VHDL Basics. Testbenches. [PPT, PDF]

Lecture 3 - RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram. [PPT, PDF]

Class Exercise 1 - STATISTICS

Class Exercise 2 - CIPHER

Lecture 2 - Digital Logic Review [PPT, PDF]

Class Exercise 1 - Combinational Logic Components

Class Exercise 2 - Sequential Logic Components

Lecture 1 - FPGA Devices and FPGA Tools [PPT, PDF]

Lecture 0 - Organization of the Course. Introduction to the Course Project. [PPT, PDF]

Viewgraphs will be posted gradually here, at least one day before a given lecture.

 

Reference Material

VHDL

VHDL Instructions: Templates & Examples

Frequently Asked Questions about VHDL from comp.lang.vhdl

OpenCores HDL Modeling Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy

vhdl.org - HDL Resources of EDA Industry Working Groups

 

Tools

The Detailed Instructions on How to Configure your FPGA Tools at School, and Install and Configure your FPGA Tools at Home (last updated 09/19/2012)

Tutorial on Simulation with Aldec Active-HDL (last updated 01/24/2012)

Tutorial on Simulation with ISim (last updated  02/01/2012)

Tutorial on Simulation with ModelSim (last updated 02/01/2012)

Simulators Reference Guide - covering Aldec Active-HDL, ModelSim, and ISim (last updated 02/01/2012)


Tutorial on FPGA Design Flow based on Aldec Active-HDL (last updated 10/27/2012)

Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ISim (last updated 10/27/2012) 

Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim (last updated 10/27/2012) 

Tutorial on Tutorial on Critical Path Analysis using Synplify Premier DP (last updated 11/18/2011)


Tutorial on Concurrent Version System based on CVS NT and Tortoise CVS

Xfig - Installation and Start-up Guide (last updated 09/25/2010)

Xfig - Export to PDF Format (last updated 12/30/2011)


Past Course Web Pages

ECE 545:     Fall 2008 (with Dr. Hwang)   Fall 2009 (with Dr. Gaj)   Fall 2010 (with Dr. Gaj)   Fall 2011 (with Dr. Gaj)

ECE 448:     Spring 2012 (with Dr. Gaj)

 

Practice and Past Exams

Final Exam 2012 - List of problem types that are likely to appear at the final exam

Midterm Exam 2012

Solutions to the Midterm Exam 2012:  Task 1, Task 1 (alternative designs for key storage), Task 2, Task 3, Task 5

Source codes for Task 4:  XTEA_pkg.vhd  ROUND.vhd


Final Exam 2011

Solutions to the Final Exam 2011:  all deliverables (zip)

Solutions to the Final Exam 2011 (selected deliverables in PDF): 

  block diagram, interface, ASM chart, short report


Midterm Exam 2011

Solutions to the Midterm Exam 2011:  [PDF, PPT]

Source codes for Task 3:  reg.vhd, ROM_16x4.vhd, main_iterative_loop.vhd

Source Codes for Task 5:  exam_top_tb.vhd

Midterm Exam 2010

Final Exam 2010


Midterm Exam 2009

Solutions to the Midterm Exam 2009: Task 1  Task 2  Task 3  Task 4

Midterm Exam 2009: Recommended Reading and Practice Problems

Final Exam 2009

Midterm Exam 1 from Fall 2006

Midterm Exam 1 from Fall 2005

Midterm Exam 1 from Fall 2004

 

Midterm Exam 2 from Fall 2006

Midterm Exam 2 from Fall 2005

Midterm Exam 2 from Fall 2004