Time and location: Thursday, 4:30-7:10 PM, The Nguyen Engineering
Building, room 1108
Tuesday 7:30-8:30PM, Thursday 7:30-8:30 PM, and by
The Engineering Building, room 3225
Thursday 7:30-8:30 PM, and by appointment
The Engineering Building, room 3231
all your homework and project reports using MyMason
by going to http://mymason.gmu.edu
the design of complex digital systems using hardware
description languages. Teaches design methodologies
which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code
for digital circuit design using dataflow,
structural, and behavioral coding styles. Introduces
VHDL simulation and verification, and FPGA
synthesis, placement, routing, timing analysis and
performance optimization. Requires semester-long
project devoted to the design of a complex digital
system implemented on FPGAs.
No official course prerequisite is required, but an
undergraduate background in digital logic design is
Pong P. Chu, RTL Hardware Design Using VHDL:
Coding for Efficiency, Portability, and Scalability,
Wiley-IEEE Press, 2006.
Circuit Design: From VLSI Architectures to CMOS
Fabrication, Cambridge University Press; 1st
Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design,
3rd Edition, McGraw-Hill, 2008.
Design and Simulation with VHDL, 2nd
Edition, The MIT Press, 2010.
Sundar Rajan, Essential
VHDL: RTL Synthesis Done Right, S & G
Peter J. Ashenden,
Designer's Guide to VHDL, 3rd
Edition, Morgan Kaufmann Publishers, 2008.
Software Packages Used in This
All software will be available in the
Computer Engineering Labs, The Engineering Building,
rooms 3208 and 3204.
Selected FREE software can be installed on your
laptops and home workstations.
(subject to possible modifications):
- Organization of the
Course. Introduction to the Course Project.
- Digital Logic Refresher. 09/06/2012
Design Methodology. Transition from Pseudocode &
Interface to a Corresponding Block Diagram. 09/13/2012
- VHDL Basics. Testbenches. 09/20/2012
- Dataflow Modeling of Combinational
- Behavioral Modeling of Sequential-Circuit
Building Blocks. Mixing
Design Styles. 10/04/2012
Devices & FPGA Device Flow. 10/11/2012
of Circuits with Regular Structure. Functions and
- Hardware Architectures of Secret-Key
Block Ciphers and Hash Functions. 11/08/2012
of Controllers. Finite State Machines and Algorithmic State Machine (ASM) Charts.
- Design of
Controllers - Examples. Alternative Coding Styles.
Modeling of Memories in FPGAs. 11/29/2012
- Project Deliverables. ATHENa
- Automated Tool for Hardware EvaluatioN. Modern
FPGA Devices. 12/06/2012
year's project will involve implementing a selected
authenticated cipher. Each student will design,
implement, and optimize one algorithm assign to
him/her by the instructor. All implementations will
be optimized using multiple criteria and implemented
using multiple families of FPGAs from Xilinx and
Altera. This project will support standardization
organizations, such as NIST, in selection of a new
authenticated encryption standard most suitable from
the point of view of hardware efficiency.
Deliverables - due Saturday,
December 15, 11:59 PM
ATHENa Database of Results
DIAC - Directions in Authenticated
GMU Source Codes and Block Diagrams of
Round 3 SHA-3 Candidates
FPGA Embedded Resources
Homework 5 - due Wednesday,
October 24, 11:59pm
- due Saturday, October 13,
Homework 3 - due
October 4, 4:30pm
2 - due Thursday, September 27, 4:30pm
Homework 1 - due Thursday, September 20, 4:30pm
with the Division into Datapath & Controller
Homework assignments will be posted gradually here, at
least 6 days before a given assignment's due date.
- ATHENa - Automated Tool for Hardware EvaluatioN.
Modern FPGA Families. [PPT,
- Memories in Xilinx FPGAs. [PPT,
- Design of Controllers. Finite State Machines
and Algorithmic State Machine (ASM) Charts.
(revised 11/29/2012, 11:55PM)
Lecture 9 -
Modeling of Circuits with a Regular Structure.
Aliases, Attributes, Functions, and Procedures. [PPT,
- Hardware Architectures of Secret-Key Block
Ciphers and Hash Functions. [PPT,
- K. Gaj
and P. Chodowiec, FPGA
and ASIC Implementations of AES, Chapter
10, in C.K. Koc (Ed.), Cryptographic Engineering
Section 10.4 Parameters of Hardware
Implementations, and Section 10.5 Hardware
Architectures of Symmetric Block Ciphers
Homsirikamol, M. Rogawski, and K. Gaj, "Throughput
vs. Area Trade-offs in High-Speed
Architectures of Five Round 3 SHA-3 Candidates
Implemented Using Xilinx and Altera FPGAs,"
in Proc. CHES 2011, Nara, Japan, pp. 491-506.
- Timing Analysis. [PPT,
Lecture 7 - FPGA Design Flow. [PPT,
6 - Behavioral Modeling of Sequential-Circuit Building
Blocks. Mixing Design Styles. [PPT,
Lecture 5 - Dataflow Modeling of Combinational Logic.
Lecture 4 - VHDL Basics.
Lecture 3 - RTL Design
Methodology. Transition from Pseudocode &
Interface to a Corresponding Block Diagram. [PPT,
Exercise 1 - STATISTICS
Exercise 2 - CIPHER
Lecture 2 - Digital Logic
Exercise 1 - Combinational Logic Components
Exercise 2 - Sequential Logic Components
Lecture 1 - FPGA Devices
and FPGA Tools [PPT,
Lecture 0 -
Organization of the Course. Introduction to the Course Project. [PPT,
Viewgraphs will be posted gradually
here, at least one day before a given lecture.
Instructions: Templates & Examples
Frequently Asked Questions about
VHDL from comp.lang.vhdl
Low Carb VHDL Tutorial - by Bryan Mealy
- HDL Resources of EDA Industry Working Groups
Past Course Web
Fall 2008 (with Dr. Hwang)
Fall 2009 (with Dr. Gaj)
Fall 2010 (with Dr.
2011 (with Dr. Gaj)
Spring 2012 (with Dr. Gaj)
Solutions to the Final Exam 2011
(selected deliverables in PDF):
to the Midterm Exam 2011: [PDF,