Time and location: Thursday, 4:307:10 PM, Robinson Hall A, room
123
Instructor:
Kris Gaj
Email: kgaj@gmu.edu
Office hours:
Tuesday 6:007:00 PM, Thursday 7:308:30 PM, and by
appointment
The Engineering Building, room 3225
TA:
Umar Sharif
Office hours:
Thursday 7:308:30 PM, and by appointment
The Engineering Building, room 3231
Email:
msharif2@masonlive.gmu.edu
Please submit
all your homework and project reports using MyMason
by going to http://mymason.gmu.edu
Course Description
Introduces
the design of complex digital systems using hardware
description languages. Teaches design methodologies
which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code
for digital circuit design using dataflow,
structural, and behavioral coding styles. Introduces
VHDL simulation and verification, and FPGA
synthesis, placement, routing, timing analysis and
performance optimization. Requires semesterlong
project devoted to the design of a complex digital
system implemented on FPGAs.
Prerequisites: Graduate
Standing.
No official course prerequisite is required, but an
undergraduate background in digital logic design is
strongly recommended.
Required Textbooks
Pong P. Chu, RTL Hardware Design Using VHDL:
Coding for Efficiency, Portability, and Scalability,
WileyIEEE Press, 2006.
Supplementary
Textbooks
Hubert
Kaeslin, Digital
Integrated
Circuit Design: From VLSI Architectures to CMOS
Fabrication, Cambridge University Press; 1st
Edition, 2008.
Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design,
3rd Edition, McGrawHill, 2008.
Volnei A.
Pedroni, Circuit
Design and Simulation with VHDL, 2nd
Edition, The MIT Press, 2010.
Sundar Rajan, Essential
VHDL: RTL Synthesis Done Right, S & G
Publishing, 1998.
Peter J. Ashenden,
The
Designer's Guide to VHDL, 3rd
Edition, Morgan Kaufmann Publishers, 2008.
Software Packages Used in This
Class
All software will be available in the
Computer Engineering Labs, The Engineering Building,
rooms 3208 and 3204.
Selected FREE software can be installed on your
laptops and home workstations.
Course Outline
(subject to possible modifications):
 Organization of the
Course. Introduction to the Course Project.
08/29/2013
 Digital Logic Refresher  Combinational Logic
Building Blocks. 09/05/2013
 Digital Logic Refresher  Sequential Logic
Building Blocks. 09/12/2013
 RTL
Design Methodology. Transition from Pseudocode &
Interface to a Corresponding Block Diagram. 09/19/2013
 VHDL Basics. 09/26/2013
 Testbenches.
Dataflow Modeling in VHDL. 10/03/2013
 Dataflow
Description of CombinationalCircuit Building Blocks
in VHDL. 10/10/2013
 Behavioral Modeling of
SequentialCircuit Building Blocks. Mixing Design Styles. Modeling
of Circuits with Regular Structure. 10/17/2013
 FPGA
Devices & FPGA Device Flow. 10/24/2013
 Midterm
Exam. 10/31/2013
 Timing Analysis (1). 11/07/2013
 Timing Analysis (2).
Design of Controllers. Finite State
Machines. 11/14/2013
 Design of
Controllers  Algorithmic State Machine (ASM)
Charts. Examples. 11/21/2013
 Design of
Controllers  Examples. Alternative
Coding Styles. Modeling
of Memories in FPGAs. ATHENa
 Automated Tool for Hardware EvaluatioN.
12/05/2013
 Final Exam. 12/12/2013
Project Resources by
Area
Area
1: Cryptography
This
year's cryptography project will involve
implementing a selected authenticated cipher, block
cipher, or stream cipher. Each student will design,
implement, and optimize one algorithm assigned to
him/her by the instructor. All implementations will
be optimized using multiple criteria and implemented
using multiple families of FPGAs from Xilinx and
Altera. This project will support standardization
organizations, such as NIST, in selection of a new
authenticated encryption standard most suitable from
the point of view of hardware efficien
The
following websites contain useful resources for
majority of cryptography projects:
Advanced Encryption Standard  AES
NIST Cryptographic Toolkit
DIAC  Directions in Authenticated
Ciphers, Stockholm 2012
DIAC  Directions in Authenticated
Ciphers, Chicago 2013
CAESAR:
Competition for Authenticated Encryption: Security,
Applicability, and Robustness
eSTREAM: the
ECRYPT Stream Cipher Project
GMU Source Codes and Block Diagrams of
Round 3 SHA3 Candidates
ATHENa Database of Results
Area
2: DSP
This
year's DSP project will involve implementing a
selected signal processing or image processing
algorithm. Each student will design, implement, and
optimize one algorithm assigned to him/her by the
instructor. All implementations will be optimized
using multiple criteria and implemented using
multiple families of FPGAs from Xilinx and Altera.
This project will serve as an introduction to the
more advanced projects pursued in the course ECE 699
Digital Signal Processing Hardware Architectures, to
be offered in Spring 2014, and every year
afterwards.
The
following books contain useful resources for
majority of DSP projects:
Common Project Resources
ATHENa Website
FPGA Embedded Resources
Homework
Homework
7  Reading
Assignment due
Thursday,
November 7,
4:30pm;
Written
Assignment due
Friday,
November 8,
11:59pm
Homework 6  Revised on Sunday, October 20,
10:30pm;
Reading
Assignment due
Thursday,
October 24,
4:30pm;
Written
Assignment due
Saturday,
October 26,
11:59pm
Homework 5  due
Monday,
October 14, 11:59pm
for full credit, or
Wednesday,
October 16, 11:59pm
with 10% penalty;
Homework
5 Hints,
Design Under Test: alu_synthesis.vhd
Homework
4  Reading
Assignment due Thursday, October
3, 4:30pm; Handson Assignment
due Saturday, October 5, 11:59pm
Homework 3 
due Thursday, September 26, 4:30pm
Homework
2  due Thursday, September 19, 4:30pm
(Problem 11 revised on Monday, September 16)
Homework
1  due Thursday, September 12, 4:30pm
Homework assignments will be posted gradually here, at
least 5 days before a given assignment's due date.
Viewgraphs
Remaining Tasks. [PPT,
PDF]
Lecture 10  FPGA Memories. ATHENa  Automated Tool for
Hardware EvaluatioN. [PPT,
PDF]
Lecture 9  Design of Controllers. Finite State Machines
and Algorithmic State Machine (ASM) Charts. [PPT,
PDF]
Examples covered in class:
STATISTICS Circuit  ASM Chart
CIPHER Circuit  ASM Chart
SORTING Circuit  ASM Chart,
Timing
Lecture 8  Timing Analysis. [PPT,
PDF]
Lecture 7  FPGA Devices and FPGA Design Flow. (extended and revised on Nov. 7, 2013)
[PPT,
PDF]
Lecture 6  Behavioral Modeling of SequentialCircuit
Building Blocks. Mixing Design Styles. Modeling of
Circuits with a Regular Structure. [PPT,
PDF]
Lecture 5  Data Flow Description of CombinationalCircuit
Building Blocks. [PPT,
PDF]
Lecture 4  Dataflow Modeling in VHDL. [PPT,
PDF]
Lecture 3  VHDL Basics. Testbenches. [PPT,
PDF]
Lecture 2  RTL Design Methodology. Transition from
Pseudocode & Interface to a Corresponding Block
Diagram [PPT,
PDF]
Examples covered in class:
STATISTICS Circuit  Specification
(solutions provided in the lecture slides)
CIPHER Circuit  Specification,
Block diagram: main
loop, memories,
Interface
divided into Datapath and Controller
Examples provided for selfstudy:
HASH Circuit  Specification,
Block
diagram, Interface
divided into Datapath and Controller
SORTING Circuit  Specification,
Analysis,
Solutions
Lecture 1B  Digital Logic Refresher. Part B  Sequential
Logic Building Blocks. [PPT,
PDF]
Lecture 1B  Digital Logic Refresher. Part B  Sequential
Logic Building Blocks. [PPT,
PDF]
Class Exercise 1B  Combinational and Sequential Logic Building
Blocks [PPT,
PDF]
Lecture 1A  Digital Logic Refresher. Part A  Combinational
Logic Building Blocks. [PPT,
PDF]
Class Exercise 1A  Combinational Logic Building Blocks [PPT,
PDF]
Lecture 0  Organization of the
Course. Introduction to the Course
Project. [PPT,
PDF]
Viewgraphs will be posted gradually
here, at least one day before a given lecture.
Reference Material
VHDL
VHDL
Instructions: Templates & Examples
Frequently Asked Questions about
VHDL from comp.lang.vhdl
OpenCores
HDL
Modeling Guidelines
The
Low Carb VHDL Tutorial  by Bryan Mealy
vhdl.org
 HDL Resources of EDA Industry Working Groups
Tools
Please see Tutorials available on the
page: Tutorials
and Lab Manuals.
Use "545" or "ECE 545" as a filter.
Past Course Web
Pages
ECE 545:
Fall
2011 Fall
2012
ECE 448:
Spring 2013
Practice
and
Past Exams
2013:
2012:
2011:
Solutions
to the Midterm Exam 2011: [PDF,
PPT]
Solutions to the Final Exam 2011
(selected deliverables in PDF):
2010:
2009:
2006:
2005:
2004:
