Time and location:

Thursday, 4:307:10 PM, Exploratory Hall, room L111

Instructor:


Email:

kgaj@gmu.edu

Office hours:

Tuesday 6:007:00 PM, Thursday 7:308:30 PM, and by
appointment
The Engineering Building, room 3225



TA:


Office hours:

Thursday 3:154:15 PM, and by appointment


The Engineering Building, room 3231

Email:

malik.umar.sharif@gmail.com

Please submit
all your homework and project reports using MyMason
by going to http://mymasonportal.gmu.edu
Please use Piazza instead of email for asking questions related to this class
Course Description
Introduces
the design of complex digital systems using hardware
description languages. Teaches design methodologies
which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code
for digital circuit design using dataflow,
structural, and behavioral coding styles. Introduces
VHDL simulation and verification, and FPGA
synthesis, placement, routing, timing analysis, and
performance optimization. Requires semesterlong
project devoted to the design of a complex digital
system implemented on FPGAs.
Prerequisites: Graduate
Standing.
No official course prerequisite is required, but an
undergraduate background in digital logic design is
strongly recommended.
Required Textbooks
Pong P. Chu, RTL Hardware Design Using VHDL:
Coding for Efficiency, Portability, and Scalability,
WileyIEEE Press, 2006.
Supplementary
Textbooks
Hubert
Kaeslin, Digital
Integrated
Circuit Design: From VLSI Architectures to CMOS
Fabrication, Cambridge University Press; 1st
Edition, 2008.
Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design,
3rd Edition, McGrawHill, 2008.
Volnei A.
Pedroni, Circuit
Design and Simulation with VHDL, 2nd
Edition, The MIT Press, 2010.
Sundar Rajan, Essential
VHDL: RTL Synthesis Done Right, S & G
Publishing, 1998.
Peter J. Ashenden,
The
Designer's Guide to VHDL, 3rd
Edition, Morgan Kaufmann Publishers, 2008.
Software Packages Used in This
Class
All software will be available in the
Computer Engineering Labs, The Engineering Building,
rooms 3208 and 3204.
Selected FREE software can be installed on your
laptops and home workstations.
Course Outline
(subject to possible modifications):
 Organization of the
Course. Introduction to the Course Project.
08/28/2014
 Digital Logic Refresher, Part A  Combinational Logic
Building Blocks. 09/04/2014
 Digital Logic Refresher, Part B  Sequential Logic
Building Blocks. RTL
Design Methodology  Part A. 09/11/2014
 RTL
Design Methodology  Part B. 09/18/2014
 VHDL Basics. Simple Testbenches. 09/25/2014
 Advanced Testbenches. 10/02/2014
 Dataflow Modeling in VHDL. Dataflow
Description of CombinationalCircuit Building Blocks
in VHDL. 10/09/2014
 Behavioral Modeling of
SequentialCircuit Building Blocks. Mixing Design Styles. Modeling
of Circuits with Regular Structure. 10/16/2014
 FPGA
Devices & FPGA Device Flow. 10/23/2014
 Midterm
Exam. 10/30/2014
 Calculating Number of Clock Cycles. Modeling
of Memories in FPGAs. FPGA Design Flow. 11/06/2014
 Poor Design Practices. Design of Controllers  Finite State
Machines. 11/13/2014
 Design of
Controllers  Algorithmic State Machine (ASM)
Charts. Examples. Alternative
Coding Styles. 11/20/2014
 Timing Analysis. Using FPGA Embedded Resources. ATHENa
 Automated Tool for Hardware EvaluatioN. Project Deliverables. 12/04/2014
 Final Exam. 12/11/2014, 4:307:15pm
Project Resources
This
year's project will involve
implementing a selected authenticated cipher competing in the CAESAR contest. Each student will design,
implement, and optimize one algorithm assigned to
him/her by the instructor. All implementations will
be optimized using multiple criteria and implemented
using multiple families of FPGAs from Xilinx and
Altera. This project will support standardization
organizations, such as NIST, in selection of a new
authenticated encryption standard most suitable from
the point of view of hardware efficiency.
AES:
Interface with the Division into the Datapath and Controller: AES_Enc, AES_EncDec, AES_Enc_KOF*
* KOF represents a version with the round keys calculated on the fly
Keccak F Permutation:
Interface with the Division into the Datapath and Controller: Keccak_F
Advanced Encryption Standard  AES
K. Gaj and P. Chodowiec, "FPGA and ASIC Implementations of AES," Chapter 10 in C.K. Koc (Ed.), Cryptographic Engineering, pp. 235320, Springer, Dec. 2008.
Examples of block diagrams for cryptographic algorithms:
The
following websites contain useful resources for
majority of cryptography projects:
CAESAR:
Competition for Authenticated Encryption: Security,
Applicability, and Robustness
NIST Cryptographic Toolkit
DIAC  Directions in Authenticated
Ciphers, Santa Barbara 2014
DIAC  Directions in Authenticated
Ciphers, Chicago 2013
DIAC  Directions in Authenticated
Ciphers, Stockholm 2012
eSTREAM: the
ECRYPT Stream Cipher Project
GMU Source Codes and Block Diagrams of
Round 3 SHA3 Candidates
ATHENa Database of Results
ATHENa Website
Homework
Homework 3  due Saturday, October 4, 11:59pm
Homework 2  due Thursday, September 25, 4:30pm
Homework 1  due Saturday, September 13, 11:59pm
Homework assignments will be posted gradually here, at
least 5 days before a given assignment's due date.
Viewgraphs
Remaining Tasks (as of 12/04/2014). [PDF]
Project Deliverables [PDF]
Verification and Result Generation. [PPT,
PDF]
Lecture 12  ATHENa  Automated Tool for Hardware EvaluatioN. [PPT,
PDF]
Lecture 11a  Controllers for Keccak_F and AES. [PPT,
PDF]
Lecture 11  Design of Controllers. Finite State Machines and Algorithmic State Machine (ASM) Charts. [PPT,
PDF]
Examples covered in class:
STATISTICS example: ASM 1, ASM 2, ASMs 1 & 2
CIPHER
example: ASMs 1 & 2, RAMs
Lecture 10b  Nonsynthesizable VHDL. Poor Design Practices. [PPT,
PDF]
Lecture 10a  Timing Analysis. Part 1. [PPT,
PDF]
Lecture 9  FPGA Design Flow. [PPT,
PDF]
Lecture 8  FPGA Memories. [PPT,
PDF]
Lecture 7  Behavioral Modeling of SequentialCircuit
Building Blocks. Mixing Design Styles. Modeling of Circuits with a
Regular Structure. [PPT,
PDF]
Lecture 6  Data Flow Description of CombinationalCircuit Building Blocks. [PPT,
PDF]
Lecture 5  Data Flow Modeling in VHDL. [PPT,
PDF]
Lecture 4  Advanced Testbenches. [PPT,
PDF]
Lecture 3  VHDL Basics. Simple Testbenches. [PPT,
PDF]
Lecture 2B  RTL Design Methodology. Transition from
Pseudocode & Interface to a Corresponding Block
Diagram [PPT,
PDF]
Example covered in class:
Class Exercise 2B  CIPHER Circuit  Specification
Solutions: block_diagram, content_of_memories, interface, variable_rotation, multiplication_mod_power_of_2
Lecture 2A  RTL Design Methodology. Transition from
Pseudocode & Interface to a Corresponding Block
Diagram [PPT,
PDF]
Example covered in class:
Class Exercise 2A  STATISTICS Circuit  Specification
(solutions provided in the lecture slides)
Lecture 1B  Digital Logic Refresher. Part B – Sequential Logic Building Blocks. [PPT, PDF]
Class Exercise 1B  Sequential Logic Building
Blocks [PPT,
PDF]
Lecture 1A  Digital Logic Refresher. Part A – Combinational Logic Building Blocks. [PPT, PDF]
Class Exercise 1A  Combinational Logic Building Blocks [PPT,
PDF]
Lecture 0  Organization of the Course. Introduction to the Course Project. [PPT, PDF]
Viewgraphs will be posted gradually
here.
Reference Material
VHDL
VHDL
Instructions: Templates & Examples
Frequently Asked Questions about
VHDL from comp.lang.vhdl
OpenCores
HDL
Modeling Guidelines
The
Low Carb VHDL Tutorial  by Bryan Mealy
vhdl.org
 HDL Resources of EDA Industry Working Groups
Tools
Please see Tutorials available on the
page: Tutorials
and Lab Manuals.
Use "545" or "ECE 545" as a filter.
Past Course Web
Pages
ECE 545:
Fall 2012 Fall
2013
ECE 448: Spring 2013 Spring 2014
Practice
and
Past Exams
2013:
2012:
2011:
Solutions
to the Midterm Exam 2011: [PDF,
PPT]
Solutions to the Final Exam 2011
(selected deliverables in PDF):
2010:
2009:
2006:
2005:
2004:
