ECE 545
Digital System Design with VHDL

Fall 2015


Time and location:

Thursday, 7:20-10:00 PM, Krug Hall, room 5

Instructor:

Kris Gaj

Email:

kgaj@gmu.edu

Office hours:

Tuesday, Thursday 6:00-7:00 PM, and by appointment

The Engineering Building, room 3225



TA:

Sanjay Deshpande

Office hours:

Tuesday 6:00-7:00 PM, Wednesday 3:00-4:00 PM, and by appointment


The Engineering Building, room 3231

Email: 

sdeshpan@masonlive.gmu.edu



Please submit all your homework and project reports using MyMason by going to http://mymasonportal.gmu.edu


Please use Piazza instead of e-mail for asking questions related to this class 


Course Description

Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis, and performance optimization. Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs. 

Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly recommended.


Required Textbooks

Pong P. ChuRTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006.

 

Supplementary Textbooks

Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Edition, McGraw-Hill, 2008.

Volnei A. Pedroni, Circuit Design and Simulation with VHDL, 2nd Edition, The MIT Press, 2010.

Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998.

Peter J. Ashenden, The Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann Publishers, 2008.
 

Software Packages Used in This Class

All software will be available in the Computer Engineering Labs, The Engineering Building, rooms 3208 and 3204.
Selected FREE software can be installed on your laptops and home workstations.

Course Outline (subject to possible modifications):

  1. Organization of the Course. Introduction to FPGA Technology.   09/03/2015
  2. Project Background.  09/10/2015
  3. Digital Logic Refresher. 09/17/2015
  4. RTL Design Methodology. 09/24/2015
  5. VHDL Basics. Simple Testbenches.  10/01/2015
  6. Block Diagrams. Modes of Operation of Block Ciphers. 10/08/2015
  7. Advanced Testbenches.  10/15/2015 
  8. Dataflow Modeling in VHDL. Dataflow Description of Combinational-Circuit Building Blocks in VHDL. 10/22/2015
  9. Behavioral Modeling of Sequential-Circuit Building Blocks. Mixing Design Styles. Modeling of Circuits with Regular Structure. 10/29/2015
  10. Midterm Exam.  11/05/2015
  11. FPGA Devices & FPGA Device Flow. Poor Design Practices. Measures of the Circuit Performance. 11/12/2015
  12. Design of Controllers - Finite State Machines and Algorithmic State Machine (ASM) Charts. 11/19/2015
  13. Design of Controllers - Alternative Coding Styles. Controllers for Keccak_F and AES. Project Deliverables.  12/03/2015
  14. Modeling of Memories in FPGAs. Using FPGA Embedded Resources. Timing Analysis. ATHENa - Automated Tool for Hardware EvaluatioN.  12/10/2015
  15. Final Exam. 12/17/2015, 7:30-10:15pm

Project Resources

This year's project will involve implementing a selected authenticated cipher competing in the CAESAR contest. Each student will design, implement, and optimize one algorithm assigned to him/her by the instructor. All implementations will be optimized using multiple criteria and implemented using multiple families of FPGAs from Xilinx and Altera. This project will support standardization organizations, such as NIST, in selection of a new authenticated encryption standard most suitable from the point of view of hardware efficiency.

The following websites contain useful resources for this year's projects:

CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness

CAESAR: Round 2 Candidates

GMU Hardware API for Authenticated Ciphers

Toward a Universal High-Speed Interface for Authenticated Ciphers, GMU presentation at CryptArchi 2015, Leuven, Belgium, June 28-July 1, 2015

GMU Supporting Materials for High-Speed Implementation of CAESAR Candidates

ATHENa Database of Results

ATHENa Website


DIAC - Directions in Authenticated Ciphers, Singapore 2015
 
DIAC - Directions in Authenticated Ciphers, Santa Barbara 2014

DIAC - Directions in Authenticated Ciphers, Chicago 2013

DIAC - Directions in Authenticated Ciphers, Stockholm 2012


NIST Cryptographic Toolkit

Advanced Encryption Standard - AES

eSTREAM: the ECRYPT Stream Cipher Project


K. Gaj and P. Chodowiec, "FPGA and ASIC Implementations of AES," Chapter 10 in C.K. Koc (Ed.), Cryptographic Engineering, pp. 235-320, Springer, Dec. 2008.

Examples of block diagrams for cryptographic algorithms:


AES:

Symbols:   AES_EncAES_EncDec, AES_Enc_KOF*, AES_Enc (RNDS=6)AES_EncDec (RNDS=6), AES_Enc_KOF (RNDS=6)

Block Diagrams of Datapaths:  AES_Enc_DatapathAES_EncDec_Datapath, AES_Enc_KOF_Datapath*, Round, InvRound, KeyUpdate

Interface with the Division into the Datapath and Controller:  AES_EncAES_EncDec, AES_Enc_KOF*

ASM Charts:  AES_Enc_ControlAES_EncDec_Control, AES_Enc_KOF_Control*

Xfig Files:  AES_symbols, AES_block_diagrams, AES_ASM_charts

* KOF represents a version with the round keys calculated on the fly


Keccak F Permutation:

Symbols:  Keccak_F, Keccak_F (RNDS=10)

Block Diagrams of the Datapath: Keccak_F_Datapath

Interface with the Division into the Datapath and Controller: Keccak_F

ASM Charts: Keccak_F_Control

Xfig Files:  Keccak_symbols, Keccak_block_diagrams, Keccak_ASM_charts

Project Recommendations - Part 1


Homework

Homework 5 - due on Saturday, Nov. 21, 2015, 11:59pm

Homework 4 (revised on Sat. Nov. 7) - due on Monday, Nov. 9, 2015, 11:59pm

Homework 3 - due on Sunday, Oct. 25, 2015, 11:59pm, extended till Thursday, Oct. 29, 6:00pm

Homework 2 - due on Thursday, Oct. 8, 2015, 7:20pm (in class)

Homework 1 - due on Saturday, Sep. 19, 2015, 11:59pm

Homework assignments will be posted gradually here, at least 5 days before a given assignment's due date.

 

Viewgraphs

Follow-up Courses [ppt, pdf]

Lecture 14 - ATHENa - Automated Tool for Hardware EvaluatioN [ppt, pdf]

ASM Chart Example: AES-COPA by Farnoud Farahmand [pdf]

GMU Hardware API for Authenticated Ciphers [pdf]

Verification and Result Generation [ppt, pdf]

Project Deliverables [pdf]

Rules for Reduced Complexity Block Diagrams, developed by William Diehl [pdf]

Lecture 13 - Controllers for Keccak_F and AES. Advanced Coding Style for Datapaths. [ppt, pdf]

Lecture 12 - Design of Controllers using Algorithmic State Machine (ASM) Charts. [ppt, pdf]

Lecture 11 - Finite State Machines Refresher. [ppt, pdf]

Lecture 10 - FPGA Design Flow. [ppt, pdf]

Lecture 9 - Behavioral Modeling of Sequential-Circuit Building Blocks. Mixing Design Styles. Modeling of Circuits with a Regular Structure. [ppt, pdf]

Lecture 8 - Data Flow Description of Combinational-Circuit Building Blocks. [ppt, pdf]

Lecture 7 - Data Flow Modeling in VHDL. [ppt, pdf]

Lecture 6 - Advanced Testbenches. [ppt, pdf]

Lecture 5B - Block Diagrams.  Hash Example. [ppt, pdf]

        Specifications of Class Exercises:  HASH

Lecture 5 - Block Diagrams. Modes of Operation of Block Ciphers. [ppt, pdf]

Lecture 4 - VHDL Basics. Simple Testbenches. [ppt, pdf]

Lecture 3 - RTL Design Methodology.  Transition from Pseudocode & Interface to a Corresponding Block Diagram. [ppt, pdf]

        Specifications of Class Exercises:  STATISTICSCIPHER

Lecture 2B - Digital Logic Refresher.  Part B Sequential Logic Building Blocks. [ppt, pdf]

Lecture 2A - Digital Logic Refresher.  Part A Combinational Logic Building Blocks. [ppt, pdf]

Lecture 1 - Project Background [ppt, pdf] (revised on Sep. 10, 2015, 7:00pm)

Lecture 0 - Organization and Introduction [ppt, pdf]

Viewgraphs will be posted gradually here.

 

Reference Material

VHDL

VHDL Instructions: Templates & Examples

Frequently Asked Questions about VHDL from comp.lang.vhdl

OpenCores HDL Modeling Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy

vhdl.org - HDL Resources of EDA Industry Working Groups

 

C

C Programming Tutorial

Top 10 C Language resources that will turn you into a better programmer

Tutorial on Recommended Integrated Development Environment for Running C Codes and Generating Test Vectors, available on the page Tutorials and Lab Manuals


Block Diagram Editors

Please see a list of recommended editors available on the page: Tools Taught in ECE Classes, and additional materials available on the page: Tutorials and Lab Manuals.


FPGA Tools

Please see Tutorials available on the page: Tutorials and Lab Manuals.

Use "545" or "ECE 545" as a filter.


Past Course Web Pages

ECE 545:     Fall 2012  Fall 2013  Fall 2014

ECE 448:     Spring 2013  Spring 2014   Spring 2015

 

Practice and Past Exams

2014:

Final Exam 2014

Solutions to the Final Exam 2014

Midterm Exam 2014 + Fill-in-the-blanks Problem 2


2013:

Final Exam 2013

Best Student Solution to Final Exam 2013

Solutions to the Problems 2A and 2B from the Final Exam 2013

Midterm Exam 2013

Solutions to the Midterm Exam 2013

2012:

Midterm Exam 2012

Solutions to the Midterm Exam 2012:  Task 1, Task 1 (alternative designs for key storage), Task 2, Task 3, Task 5

Source codes for Task 4:  XTEA_pkg.vhd  ROUND.vhd

Final Exam 2012

Best Student Solution to Final Exam 2012

2011:

Midterm Exam 2011

Solutions to the Midterm Exam 2011:  [PDF, PPT]

Source codes for Task 3:  reg.vhd, ROM_16x4.vhd, main_iterative_loop.vhd

Source Codes for Task 5:  exam_top_tb.vhd


Final Exam 2011

Solutions to the Final Exam 2011:  all deliverables (zip)

Solutions to the Final Exam 2011 (selected deliverables in PDF): 

  block diagram, interface, ASM chart, short report


2010:

Midterm Exam 2010

Final Exam 2010

Best Student Solution to Final Exam 2010


2009:

Midterm Exam 2009

Solutions to the Midterm Exam 2009: Task 1  Task 2  Task 3  Task 4

Midterm Exam 2009: Recommended Reading and Practice Problems


Final Exam 2009


2006:

Midterm Exam 1 from Fall 2006

Midterm Exam 2 from Fall 2006

2005:

Midterm Exam 1 from Fall 2005

Midterm Exam 2 from Fall 2005

2004:

Midterm Exam 1 from Fall 2004

Midterm Exam 2 from Fall 2004