ECE 545
Digital System Design with VHDL

Fall 2017

Time and location:

Thursday, 4:30-7:10 PM


Kris Gaj


Office hours:

Thursday 3:15-4:15 PM, Tuesday 6:00-7:00 PM, and by appointment

The Engineering Building, room 3225


Farnoud Farahmand

Office hours:

Tuesday, 7:00-9:00 PM, Wednesday 10:00 AM - 12:00 PM

The Engineering Building, room 3204


Please submit all your homework and project reports using MyMason by going to

Please use Piazza instead of e-mail for asking questions related to this class 

Course Description

Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis, and performance optimization. Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs. 

Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly recommended.

Required Textbooks

Pong P. ChuRTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006.

Supplementary Textbooks

Ricardo Jasinski, Effective Coding with VHDL: Principles and Best Practice, 1st Edition, The MIT Press, 2016.

Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Edition, McGraw-Hill, 2008.

Volnei A. Pedroni, Circuit Design and Simulation with VHDL, 2nd Edition, The MIT Press, 2010.

Peter J. Ashenden, The Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann Publishers, 2008.

Software Packages Used in This Class

  • Xilinx Vivado Design Suite

  • ModelSim Intel FPGA

Full versions of these packages will be available in the Computer Engineering Labs, The Engineering Building, rooms 3208 and 3204.
FREE versions can be installed on your laptops and home workstations.

Course Outline (subject to possible modifications):

  1. Organization of the Course. Introduction to FPGA Technology. Project.  08/31/2017
  2. Digital Logic Refresher - Combinational Logic.  09/07/2017
  3. Digital Logic Refresher - Sequential Logic.  09/14/2017
  4. RTL Design Methodology - Part 1. HDL Basics. 09/21/2017
  5. RTL Design Methodology - Part 2. Fundamentals of VHDL. 09/28/2017
  6. VHDL Testbenches.  
  7. Dataflow Modeling in VHDL. Dataflow Description of Combinational-Circuit Building Blocks in VHDL. 
  8. Behavioral Modeling of Sequential-Circuit Building Blocks. Mixing Design Styles. Modeling of Circuits with Regular Structure. 
  9. Midterm Exam.  
  10. FPGA Devices & FPGA Device Flow. Poor Design Practices. Measures of the Circuit Performance
  11. Design of Controllers - Finite State Machines and Algorithmic State Machine (ASM) Charts
  12. Design of Controllers - Alternative Coding Styles. Controllers for Keccak_F and AES. Project Deliverables. 
  13. Modeling of Memories in FPGAs. Using FPGA Embedded Resources. Timing Analysis. 
  14. Final Exam. 12/14/2017, 4:30-7:15pm


This year's project will involve implementing a selected post-quantum cryptosystem (or its sub-function). Each group of students will design, implement, and optimize one algorithm assigned to them by the instructor or proposed by themselves. All implementations will be optimized using multiple criteria and implemented using multiple families of Xilinx FPGAs. This project will support standardization organizations, such as NIST, in selection of new standards resistant against quantum computers.


Homework 2, due Thursday, September 21, 4:30pm

Homework 1, due Thursday, September 14, 4:30pm

Homework assignments will be posted gradually here, at least 5 days before a given assignment is due.


[pdf-1: 1 slide per page, pdf-6: 6 slides per page]

Lecture 3 - HDL Basics. [pdf-1, pdf-6]

Lecture 2A - RTL Design Methodology. Transition from the Pseudocode & Interface to a Corresponding Block Diagram. [pdf-1, pdf-6]

Lecture 1B - Digital Logic Refresher. Part B Sequential Logic Building Blocks. [pdf-1, pdf-6]

Class Exercise 1B - Combinational Logic Building Blocks [pdf-1, pdf-6]

Lecture 1A - Digital Logic Refresher. Part A Combinational Logic Building Blocks. [pdf-1, pdf-6]

Class Exercise 1A - Combinational Logic Building Blocks [pdf-1, pdf-6]

Lecture 0 - Organization and Introduction [pdf-1, pdf-6]

Viewgraphs will be posted gradually here.


Reference Material


VHDL Instructions: Templates & Examples

OpenCores HDL Modeling Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy



Top 10 C Language resources that will turn you into a better programmer

Tutorial on Recommended Integrated Development Environment for Running C Codes and Generating Test Vectors, available on the page Tutorials and Lab Manuals

Block Diagram Editors

Please see a list of recommended editors available on the page: Tools Taught in ECE Classes, and additional materials available on the page: Tutorials and Lab Manuals.

Past Course Web Pages

ECE 545:    Fall 2015  Fall 2014  Fall 2013  Fall 2012 

ECE 448:    Spring 2015  Spring 2014  Spring 2013 


Practice and Past Exams


Final Exam 2015

Midterm Exam 2015


Final Exam 2014

Solutions to the Final Exam 2014

Midterm Exam 2014 + Fill-in-the-blanks Problem 2


Final Exam 2013

Best Student Solution to Final Exam 2013

Solutions to the Problems 2A and 2B from the Final Exam 2013

Midterm Exam 2013

Solutions to the Midterm Exam 2013


Midterm Exam 2012

Solutions to the Midterm Exam 2012:  Task 1, Task 1 (alternative designs for key storage), Task 2, Task 3, Task 5

Source codes for Task 4:  XTEA_pkg.vhd  ROUND.vhd

Final Exam 2012

Best Student Solution to the Final Exam 2012


Midterm Exam 2011

Solutions to the Midterm Exam 2011:  [PDF, PPT]

Source codes for Task 3:  reg.vhd, ROM_16x4.vhd, main_iterative_loop.vhd

Source Codes for Task 5:  exam_top_tb.vhd

Final Exam 2011

Solutions to the Final Exam 2011:  all deliverables (zip)

Solutions to the Final Exam 2011 (selected deliverables in PDF): 

  block diagram, interface, ASM chart, short report


Midterm Exam 2010

Final Exam 2010

Best Student Solution to Final Exam 2010


Midterm Exam 2009

Solutions to the Midterm Exam 2009: Task 1  Task 2  Task 3  Task 4

Midterm Exam 2009: Recommended Reading and Practice Problems

Final Exam 2009


Midterm Exam 1 from Fall 2006

Midterm Exam 2 from Fall 2006


Midterm Exam 1 from Fall 2005

Midterm Exam 2 from Fall 2005


Midterm Exam 1 from Fall 2004

Midterm Exam 2 from Fall 2004