Time and location:
Thursday 3:15-4:15 PM, Tuesday 6:00-7:00 PM, and by appointment
Engineering Building, room 3225
Tuesday, 7:00-9:00 PM, Wednesday 10:00 AM - 12:00 PM
Engineering Building, room 3204
Please submit all your homework and project reports using
going to http://mymasonportal.gmu.edu
Please use Piazza instead of e-mail
for asking questions related to this class
the design of
complex digital systems using hardware description languages. Teaches
design methodologies which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code for digital circuit
design using dataflow, structural, and behavioral coding styles.
Introduces VHDL simulation and verification, and FPGA synthesis,
placement, routing, timing analysis, and performance optimization.
Requires semester-long project devoted to the design of a complex
digital system implemented on FPGAs.
Standing. No official course prerequisite is required, but an
undergraduate background in digital logic design is strongly
Pong P. Chu, RTL Hardware Design Using VHDL: Coding for
Efficiency, Portability, and Scalability, Wiley-IEEE Press,
Coding with VHDL: Principles and Best Practice, 1st Edition, The
MIT Press, 2016.
Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication,
Cambridge University Press; 1st Edition, 2008.
Stephen Brown and Zvonko
Fundamentals of Digital Logic with VHDL Design, 3rd Edition,
Volnei A. Pedroni,
Design and Simulation with VHDL, 2nd Edition, The MIT Press,
Peter J. Ashenden, The
Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann
Software Packages Used in This Class
Xilinx Vivado Design Suite
- ModelSim Intel FPGA
Full versions of these packages will be available in the Computer Engineering Labs, The
Engineering Building, rooms 3208 and 3204.
FREE versions can be installed on your laptops and home
Course Outline (subject to
- Organization of the Course. Introduction
to FPGA Technology. Project. 08/31/2017
Logic Refresher - Combinational Logic. 09/07/2017
Logic Refresher - Sequential Logic. 09/14/2017
- RTL Design Methodology - Part 1. HDL
- RTL Design Methodology - Part 2. Fundamentals of VHDL. 09/28/2017
- VHDL Testbenches.
Modeling in VHDL. Dataflow Description of Combinational-Circuit
Building Blocks in VHDL.
- Behavioral Modeling of Sequential-Circuit
Building Blocks. Mixing Design Styles. Modeling of
Circuits with Regular Structure.
- FPGA Devices
& FPGA Device Flow. Poor Design Practices. Measures of the
- Design of
Controllers - Finite State Machines and Algorithmic State Machine (ASM) Charts.
- Design of
Controllers - Alternative Coding
Styles. Controllers for Keccak_F and AES. Project Deliverables.
of Memories in FPGAs. Using FPGA Embedded Resources. Timing
- Final Exam. 12/14/2017, 4:30-7:15pm
This year's project will
involve implementing a selected post-quantum cryptosystem (or its
sub-function). Each group of students will design, implement, and
algorithm assigned to them by the instructor or proposed by themselves.
will be optimized using multiple criteria and implemented using
multiple families of Xilinx FPGAs. This project will
support standardization organizations, such as NIST, in selection of
new standards resistant against quantum computers.
Homework 2, due Thursday, September 21, 4:30pm
Homework 1, due Thursday, September 14, 4:30pm
Homework assignments will be posted
gradually here, at least 5 days before a given assignment is due.
[pdf-1: 1 slide per page, pdf-6: 6 slides per page]
Lecture 3 - HDL Basics. [pdf-1, pdf-6]
Lecture 2A - RTL Design Methodology. Transition from the Pseudocode & Interface to a Corresponding Block Diagram. [pdf-1, pdf-6]
Lecture 1B - Digital Logic Refresher. Part B – Sequential Logic Building Blocks. [pdf-1, pdf-6]
Class Exercise 1B - Combinational Logic Building Blocks [pdf-1, pdf-6]
Lecture 1A - Digital Logic Refresher. Part A – Combinational Logic Building Blocks. [pdf-1, pdf-6]
Class Exercise 1A - Combinational Logic Building Blocks [pdf-1, pdf-6]
Lecture 0 - Organization and Introduction [pdf-1, pdf-6]
Viewgraphs will be posted gradually here.
VHDL Instructions: Templates
HDL Modeling Guidelines
The Low Carb VHDL Tutorial
- by Bryan Mealy
Tutorial on Recommended
Integrated Development Environment for Running C Codes and Generating
Test Vectors, available on the page Tutorials and Lab
Block Diagram Editors
Please see a list of recommended editors
available on the page: Tools Taught in
ECE Classes, and additional materials available on the page: Tutorials and Lab
Past Course Web Pages
ECE 448: Spring 2015
and Past Exams
Solutions to the Midterm Exam 2011: [PDF, PPT]
Solutions to the Final Exam 2011 (selected deliverables