Time and location:

Thursday,
4:307:10 PM

Instructor:


Email:

kgaj@gmu.edu

Office hours:

Thursday
3:154:15 PM, Tuesday 6:007:00 PM, and by appointment
The
Engineering Building, room 3225



TA:


Office hours:

Tuesday,
7:009:00 PM, Wednesday 10:00 AM  12:00 PM


The
Engineering Building, room 3204

Email:

ffarahma@masonlive.gmu.edu

Please submit all your homework and project reports using
MyMason
by
going to http://mymasonportal.gmu.edu
Please use Piazza instead of email
for asking questions related to this class
Course Description
Introduces
the design of
complex digital systems using hardware description languages. Teaches
design methodologies which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code for digital circuit
design using dataflow, structural, and behavioral coding styles.
Introduces VHDL simulation and verification, and FPGA synthesis,
placement, routing, timing analysis, and performance optimization.
Requires semesterlong project devoted to the design of a complex
digital system implemented on FPGAs.
Prerequisites: Graduate
Standing. No official course prerequisite is required, but an
undergraduate background in digital logic design is strongly
recommended.
Required Textbooks
Pong P. Chu, RTL Hardware Design Using VHDL: Coding for
Efficiency, Portability, and Scalability, WileyIEEE Press,
2006.
Supplementary Textbooks
Ricardo
Jasinski, Effective
Coding with VHDL: Principles and Best Practice, 1st Edition, The
MIT Press, 2016.
Hubert
Kaeslin, Digital
Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication,
Cambridge University Press; 1st Edition, 2008.
Stephen Brown and Zvonko
Vranesic,
Fundamentals of Digital Logic with VHDL Design, 3rd Edition,
McGrawHill, 2008.
Volnei A. Pedroni,
Circuit
Design and Simulation with VHDL, 2nd Edition, The MIT Press,
2010.
Peter J. Ashenden, The
Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann
Publishers, 2008.
Software Packages Used in This Class

Xilinx Vivado Design Suite
 ModelSim Intel FPGA
Full
versions of these packages will be available in the Computer
Engineering Labs, The
Engineering Building, rooms 3208 and 3204.
FREE versions can be installed on your laptops and home
workstations.
Course Outline (subject to
possible modifications):
 Organization of the Course. Introduction
to FPGA Technology. Project. 08/31/2017
 Digital
Logic Refresher  Combinational Logic. 09/07/2017
 Digital
Logic Refresher  Sequential Logic. 09/14/2017
 RTL
Design Methodology  Part 1. HDL
Basics. 09/21/2017
 RTL
Design Methodology  Part 2. Fundamentals of VHDL. 09/28/2017
 VHDL Testbenches. 10/05/2017
 Advanced
Testbenches. Dataflow
Modeling in VHDL. 10/12/2017
 Dataflow Description of
CombinationalCircuit
Building Blocks in VHDL. Behavioral Modeling of SequentialCircuit
Building Blocks.
Mixing Design Styles. 10/19/2017
 Modeling of
Circuits with Regular Structure. Poor
Design Practices. Measures of the
Circuit Performance. 10/26/2017
 Midterm
Exam. 11/02/2017
 Finite State
Machines. Designing Controllers using Algorithmic State Machine (ASM)
charts. 11/09/2017
 Design of
Controllers using ASM Charts. 11/16/2017
 Modeling
of Memories in FPGAs. Using FPGA Embedded Resources. Project Recommendations & Deliverables. 11/30/2017
 Timing
Analysis. FPGA Devices
& FPGA Device Flow. Optimization of Tool
Options. 12/07/2017
 Final Exam  Takehome. 12/14/2017, 4:3010:30pm
Project
This year's project will
involve implementing a selected postquantum cryptosystem (or its
subfunction). Each group of students will design, implement, and
optimize one
algorithm assigned to them by the instructor or proposed by themselves.
All implementations
will be optimized using multiple criteria and implemented using
multiple families of Xilinx FPGAs. This project will
support standardization organizations, such as NIST, in selection of
new standards resistant against quantum computers.
Project Recommendations
Project Deliverables
Reduced Complexity Block Diagrams
Examples of 5port Wrappers
Homework
Homework 7,
due
Thursday, November 30, 2:00pm
Homework 6,
due
Saturday, October 21, 11:59pm (revised on
10/20/17) + synthesizable
code of ALU
Homework 5,
due Saturday, October 14, 11:59pm (revised on 10/20/17)
Homework 4,
due Saturday, October 7, 11:59pm
Homework 3,
due Friday, September 29, 12:00pm
Homework 2,
due Thursday, September 21, 4:30pm
Homework 1,
due Thursday, September 14, 4:30pm
Homework assignments will be posted
gradually here, at least 5 days before a given assignment is due.
Viewgraphs
[pdf1: 1 slide per page, pdf6: 6 slides
per page]
Remaining Tasks. [pdf1, pdf6]
Lecture 13  Timing Analysis. [pdf1, pdf6]
Lecture 12  FPGA Resources. [pdf1, pdf6]
Lecture 11  Programmable Logic Memories. [pdf1, pdf6]
Lecture 10  Design of Controllers using
ASM Charts. [pdf1, pdf6]
Lecture 9  Finite State Machines.
Designing Controllers using Algorithmic State Machine (ASM) charts. [pdf1,
pdf6] (revised on 11/10/17)
Lecture 8  Modeling of Circuits with a
Regular Structure. [pdf1, pdf6]
Lecture 7  VHDL Description of Basic
Combinational & Sequential Circuit Building Blocks. [pdf1,
pdf6] (revised on 10/20/17)
Lecture 6  Dataflow Modeling in VHDL. [pdf1,
pdf6]
Lecture 5  Testbenches. [pdf1,
pdf6] (extended on 10/13/17)
ECE545_F17_testbenches_1.zip
ECE545_F17_testbenches_2.zip
Lecture 4  VHDL Fundamentals. [pdf1, pdf6]
Lecture 2B  RTL Design Methodology.
CIPHER example. [pdf1,
pdf6]
CIPHER example 
specification
Lecture 3  HDL Basics. [pdf1,
pdf6]
Lecture 2A  RTL Design Methodology.
STATISTICS example. [pdf1, pdf6]
STATISTICS
example  specification
Lecture 1B  Digital Logic Refresher.
Part B – Sequential Logic Building Blocks. [pdf1,
pdf6]
Class
Exercise 1B  Combinational Logic Building Blocks [pdf1, pdf6]
Lecture 1A  Digital Logic Refresher.
Part A – Combinational Logic Building Blocks. [pdf1,
pdf6]
Class
Exercise 1A  Combinational Logic Building Blocks [pdf1, pdf6]
Lecture 0  Organization and
Introduction [pdf1, pdf6]
Viewgraphs will be posted gradually here.
Reference Material
VHDL
VHDL Instructions: Templates
& Examples
OpenCores
HDL Modeling Guidelines
The Low Carb VHDL Tutorial
 by Bryan Mealy
C
Tutorial on Recommended
Integrated Development Environment for Running C Codes and Generating
Test Vectors, available on the page Tutorials and Lab
Manuals
Block Diagram Editors
Please see a list of recommended editors
available on the page: Tools Taught in
ECE Classes, and additional materials available on the page: Tutorials and Lab
Manuals.
Past Course Web Pages
ECE 545:
Fall 2015
Fall 2014
Fall 2013
Fall 2012
ECE 448: Spring
2015 Spring 2014
Spring 2013
Practice
and Past Exams
2017:
2015:
2014:
2013:
2012:
2011:
Solutions to the Midterm Exam 2011: [PDF, PPT]
Solutions to the Final Exam 2011 (selected deliverables
in PDF):
2010:
2009:
2006:
2005:
2004:
