Based on the partial solution distributed in class, design simple combinational circuits capable of rounding a signed number in the two's complement representation with 12-bits in the integer part and 4 bits in the fractional part to a 12-bit integer, using the following schemes:
a. rounding toward nearest, half-up, asymmetric implementation
b. rounding toward nearest, half-up, symmetric implementation
c. rounding to nearest even (banker's rounding)
d. rounding towards +infinity (upward, round-ceiling)
e. rounding towards -infinity (downward, round-floor)
f. rounding towards zero (inward)
g. rounding away from zero (outward)
Each circuit, apart from the 12-bit integer output, should contain also an overflow output.
Implement all these circuits in VHDL, using generics to denote the number of bits in the integer and the fractional part of an input.
Synthesize and implement the obtained codes, and compare them in terms of the number of CLB slices and latency in ns.