Implement using synthesizable VHDL (or Verilog) the following two 256-bit adders:
A. Carry-Lookahead Adder
B. Multilevel Carry Select Adder based on 32-bit Ripple Carry Adders.
Synthesize and implement both adders targeting
Xilinx Spartan 3 FPGAs.
Perform static timing analysis after placing and routing, and determine the minimum latency and critical path of both adders.
Optimize both adders for minimum latency.
Compare the latency (in ns) and area (in the number of CLB slices) of each of these two adders vs. the latency and area of a default adder implemented using a "+" sign in VHDL (or Verilog).
Design Requirements
Your VHDL code for
EACH adder should consists of three
levels of the design hierarchy
I. synthesizable code of an adder itself with a clearly defined adder
boundary,
II. synthesizable test circuit with ALL inputs and outputs of an adder
stored in registers in order to facilitate static timing
analysis of your circuit during implementation,
III. non-synthesizable testbench.
All
adder types
- should have the same entity declaration at level I
- share the test circuit at level II,
- share the testbench at level III
- use different test vector files at level III.
The total numbers of inputs and outputs of your circuit at level II should be limited by the total number of i/o pins available in the smallest Xilinx Spartan 3 device capable of holding the adder (Hint: You can use, for example, 32-bit input data bus to load data to the operand registers and 32-bit output data bus to read out the contents of the output register).
Dataflow description is a preferred design style for synthesizable portions of your code. Use behavioral description only if necessary (e.g., for description of flip-flops and registers).
Behavioral description is a preferred design style for your testbenches. Your testbenches should stimulate circuit inputs using multiple representative test vectors read from a file common for all adder types.
Deliverables (submitted using Blackboard):
For the implemented adders:
1. ALL source files you have developed as a part of the project
2. test vectors, and a short description how these test vectors were generated. Hint: You may use software (your own or public domain) to generate your test vectors. Your test vectors should be different for each adder, and should be chosen in such a way to trigger the most critical path of a respective adder.
3. waveforms from the timing simulation (after placing and routing) demonstrating the correct operation of each circuit for test vectors triggering the most critical path in a given adder
4. full reports from static timing analysis
5. one table summarizing the relative performance of each of the implemented adders in terms of
minimum latency
speed up in terms of latency compared to an adder implemented using a "+" sign
area
area increase vs. an adder implemented using a "+" sign
number of lines of VHDL code at level I
product latency * area