Project 2 - Phase 4 (final)

All deliverables for Phases 1-4 due Sunday, May 3, 23:59 PM.

Implement using synthesizable VHDL (or Verilog) the following two signed integer dividers with the dividend size 2k bits and the divisor size k bits

Option I

a. Sequential Radix-2 Restoring Signed Integer Divider

b. Sequential Non-restoring Radix-2 Signed Integer Divider

a. Array Restoring Signed Integer Divider

b. Array Non-restoring Signed Integer Divider

Optimize your designs from Option I for the minimum product of latency times area.

Optimize your designs from Option II for the minimum latency.

Your circuits should operate correctly for arbitrary values of the parameter k.

All dividers should report an overflow using a separate output V. Assume that in case of an overflow, the value of the quotient and the remainder is undetermined.

Task 6 (Bonus 4 points)

Implement using synthesizable VHDL (or Verilog) the following unsigned integer divider with the dividend size 2k bits and the divisor size k bits.

   Unsigned Radix-2 Fractional Divider with Partial Remainder Stored in the Carry Save Form (Parhami, Fig. 14.8)

Verification, Synthesis, and Implementation

Verify your designs first for k=8, and then synthesize and implement them for k=64 (or k=32 if you have chosen Option II and array dividers for k=64 do not fit within Xilinx Spartan 3).

• Xilinx Spartan 3 FPGAs.

All reported performance measures (latency, throughput, area) should be calculated after placing and routing.

Design Requirements

1. Your VHDL code for EACH divider should consists of three levels of the design hierarchy
     I. synthesizable code of a divider itself with a clearly defined divider boundary,
    II.  synthesizable test circuit with ALL inputs and outputs of a divider stored in registers in order to facilitate static timing analysis of your circuit during implementation,
    III. non-synthesizable testbench.

2. All divider types
    - should have the same entity declaration at level I
    - share the test circuit at level II,
    - share the testbench at level III
    - use different test vector files at level III.

3. The total numbers of inputs and outputs of your circuit at level II should be limited by the total number of i/o pins available in the smallest Xilinx Spartan 3 device capable of holding the divider (Hint: You can use, for example, 32-bit input data bus to load data to the operand registers and 32-bit output data bus to read out the contents of the output register).

4. Dataflow description is a preferred design style for synthesizable portions of your code. Use behavioral description only if necessary (e.g., for description of flip-flops and registers).

5. Behavioral description is a preferred design style for your testbenches. Your testbenches should stimulate circuit inputs using multiple representative test vectors read from a file common for all multiplier types.

Deliverables (submitted using Blackboard):

For the implemented dividers:

1. ALL source files you have developed as a part of the project

2. test vectors, and a short description how these test vectors were generated. Hint: You may use software (your own or public domain) to generate your test vectors. Your test vectors should be different for each divider, and should be chosen in such a way to trigger the most critical path of a respective divider

3. waveforms from the timing simulation (after placing and routing) demonstrating the correct operation of each circuit for test vectors triggering the most critical path in a given divider

4. full reports from static timing analysis

5. one table summarizing your results for all implemented dividers: 

• minimum clock period
• minimum latency
  
• area in CLB slices 
• product latency * area
• maximum throughput
• ratio throughput/area
• number of lines of VHDL code at level I.

• minimum clock period
• minimum latency
  
• area in CLB slices 
• product latency * area
• maximum throughput
• ratio throughput/area
• number of lines of VHDL code at level I.