Homework 3

Required reading


Chapter 1, Numbers and Arithmetic, Sections 1.1-1.6.

Chapter 2, Representing Signed Numbers, Sections 2.1-2.6.


Recommended reading (material covered during the next class)


Chapter 17, Floating-point Representations.


                IEEE 754-2008

Written Assignment

Due Monday, March 26

Problem 1

Develop a pipelined implementation of a 32-bit Hybrid Brent-Kung/Kogge-Stone Parallel Prefix Network Adder.

Optimize a total number of pipeline stages in your design for the best Throughput to Area ratio.

Compare your non-pipelined adder with the corresponding pipelined adder in terms of the Throughput, Area, and Throughput to Area Ratio for k=32.

Problem 2

a. Determine how many digits are necessary to represent all possible values of the 

     A. sum of 64 integers in the range from 0016 to FF16 each
     B. product of 100
integers in the range from 0 to 99 each

    - radix-2 conventional system
    - radix-10 conventional system
    - radix-16 conventional system

b. Represent the following decimal numbers in hexadecimal representation.

    864.6328125,   1567.19140625

c. Convert the following octal (radix-8) numbers to hexadecimal (radix-16) notation:


d. Represent    -109.7109375 and -71.2890625
    using the following binary signed number representations
k = 8 and l = 8

    - signed magnitude
    - one's complement

    - two's complement
    - biased with the base B=128.

e. Extend all numbers from point d., expressed in the respective signed number representations with k = 8 and l = 8, to the numbers with the same value and the sizes of the integer and fractional part equal respectively to k' = 16 and l' = 16. (Hint: Apply formulas from Lecture 1, slide 70, "Extending the number of bits of a signed number"). Convert the obtained numbers to the decimal representation and show that they have the same value as numbers you started with in point e.

Problem 3 (bonus)

Prove a formula for an extension of a signed number in the biased representation  with a k-bit integer part and an l-bit fractional part to a number with a k'-bit integer part and an l'-bit fractional part, with k' > k and l' > l (see Lecture 1, slide 70, "Extending the number of bits of a signed number").

Problem 4 (bonus)

Find the contents of LUT F and LUT G in the implementation of a 5-to-3 parallel counter using a single CLB slice of a Virtex FPGA (see slides from Lecture 4).