GMU FPGA CAD Tools at School and Home

(Last updated: Jan 24, 2012. Report bugs to Umar Sharif (msharif2@masonlive.gmu.edu) and Ambarish Vyas (avyas2@gmu.edu))

 

CAD tools at school

In GMU FPGA-related courses you have an option of using three different design environments:

All three environments can be used to invoke all necessary FPGA tools: a simulator, synthesis tool, and implementation tool.


The following is a short description of three aforementioned environments available at school in the Engineering Building rooms
3204 and 3208. Note that the machines in these rooms may have several different versions of tools installed on them. Please use versions of tools specified below unless your instructor recommends otherwise.

Option 1: Aldec Environment (School)

GUI/IDE: Aldec Active-HDL 9.1 SP 1
VHDL Simulator: Aldec Active-HDL 9.1 SP 1
Synthesis: Xilinx XST 13.3 or
Synplify Premier DP F-2011-09
Implementation: Xilinx ISE 13.3

How to set up Aldec Environment (School)

  1. When you open Aldec Active-HDL for the first time in the lab, initialize the environment to point to the correct tools (these settings may have been set already by default).

    1. Go to: Tools...Preferences. In the window that appears, go to Environment => Flows => Integrated Tools.

    2. For HDL Synthesis, you can choose one of the two options. i.e., Xilinx XST 13.3 or Synplify Premier DP.
    3. Go to Tools => Preferences. In this category, expand Flows => Integrated Tools.

    4. For Synplify Premier DP, Click "browse", Under the category "Synopsis", select "Synplify Premier DP F-2011-09".

    5. For Xilinx XST, browse to "Xilinx/13.3/ISE/bin/nt/xst.exe".
    6. For Implementation, push "Select" and choose Xilinx ISE 13.3.

    7. For Family, choose the family used in a given project. For example, selecting "Xilinx 11x Virtex5" sets the default family as Virtex5. Selecting "Xilinx 11x Spartan3" sets the default family as Spartan3.

    8. Push "OK" to save changes.

Option 2: Xilinx Environment (School)

GUI/Environment: Xilinx ISE 13.3
VHDL Simulator: ModelSim SE 10.0b
Synthesis: Xilinx XST 13.3
Implementation: Xilinx ISE 13.3

How to set up Xilinx Environment (School)

  1. When you open a new project in Xilinx ISE Foundation for the first time, initialize the environment to point to the correct tools.

    1. Go to File...New Project. Set a project name and push "Next."

    2. For Product Category, choose "All."

    3. For Family, choose the default family. For example, "Virtex5" or "Spartan3."

    4. For Synthesis tool, choose "XST (VHDL/Verilog)."

    5. For Simulator, choose "ModelSim-SE VHDL."

    6. For Preferred Language, choose "VHDL."

    7. Push "Next" and choose the rest of your options (by default, continue to push "Next" without making changes) until you push "Finish."

Option 3: Altera Environment (School)

GUI/Environment: Altera Quartus II 11.0
VHDL Simulator: ModelSim-Altera 6.6d
Synthesis: Altera Quartus II Integrated Synthesis (QIS) 11.0
Implementation:
Altera Quartus II Integrated Synthesis (QIS) 11.0, Fitter

How to set up Altera Environment (School)

  1. When you open a new project in Altera Quartus II for the first time, initialize the environment to point to the correct tools.

    1. Go to File..."New Project Wizard"and push "Next."
    2. For the Working Directory of the Project, choose Directory Name of your choice.

    3. Choose a "Name of the Project" and enter "Name of the Top-Level Design Entity" and Push "Next".
    4. In the next Window, specify all existing files (if you have any),  select "Add All" and push "Next".

    5. For Family, choose the family. For example, "Cyclone II" or "Stratix III" and push "Next".
    6. Under EDA Tools, enter "Modelsim-Altera" for "Simulation" and select "Next".

    7. Push "Next" and choose the rest of your options (by default, continue to push "Next" without making changes) until you push "Finish."
    8. Once you have the complete VHDL source files for your design, Select "Compile Design" under "Task" to perform "Analysis & Synthesis" followed by "Fitter (Place & Route)".


CAD tools at home

Majority of students like the flexibility of working from home. Aldec and Xilinx provide free tools to students as described below. However be forewarned: these tools often carry feature limitations and may run much slower than full versions of tools installed at school. Please investigate the vendor websites to understand the limitations of these tools in detail.

Since the tools are not exactly the same at school and at home, you may run into some discrepancies or incompatibilities. If you are working from home and from school, be sure to save a copy of your source files NOT the project folder before trying to transfer from the home environment to the school environment or vice-versa, especially if you are Aldec user. This would eliminate the incompatibility issues that may arise from different version of tools and computer. Note that you may need to create a new project for each transfer of data.

If you work from home, for compatibility reasons, here are the configurations you are recommended to use. Details on how to download and install software to attain these configurations are given below. Again, as with the school computers, you can choose either the Aldec Environment, Xilinx Environment or Altera Environment. 

All tools run on Windows XP, Windows Vista and Windows 7 operating systems.

If you have problems with the software running on your personal computers, the best solution is to use the computers in the lab at school.


Option 1: Aldec Environment (Home)

GUI Environment: Aldec Active-HDL Student Edition 7.2
VHDL Simulator: Aldec Active-HDL Student Edition 7.2
Synthesis: Xilinx ISE/Webpack XST 9.1 SP3
Implementation: Xilinx ISE/Webpack 9.1 SP3

1. Download and install Aldec Active-HDL Student Edition

    1. Go to the Aldec Webpage and click "Download." Then click on "Register". Make sure to use your GMU Email ID to register.

    2. Once you Register, you will have to wait for 24 hours before your account is approved and verified. Follow the instructions to login.

    3. When you successfully login, Click "Downloads". Then click "Accept". You will see a webpage with title "Latest Builds and Libraries". Click on "Request Eval License" on the right corner. Enter your MAC address and hit "Submit".
    4. Wait for another email from Aldec with a download link for Aldec Active-HDL Student Edition 7.2.
    5. Install the following libraries for Aldec Student Edition from the same webpage.
      • Download and install Xilinx VHDL Libraries ISE 9.1 SP3 with IP Update 2 for Active-HDL 7.2 Student Edition.

      • Download and install Xilinx Schematic Libraries ISE 8.2 SP3 for Active-HDL 7.2 Student Edition.

    2. Download and install Xilinx Webpack 9.1 SP3. Follow the steps below.

    1. Go to   Xilinx ISE Classics
    2. Download and install "WebPACK_9.1i_SFD." ISE Webpack is a feature-limited version of ISE Foundation (i.e., the largest FPGA device in a family is not supported) 
    3. Note: If you have Windows 7 Operating System go to the folder bin/nt and run setup.exe located in this folder to install ISE Webpack.
    4. Go to Xilinx ISE Download, click on Archive, and choose 9.1 SP3 and download the service pack for Windows.

3. When you open Aldec Active-HDL Student Edition for the first time, initialize the environment to point to the correct tools.

  1. Go to: Tools =>Preferences. In the window that appears, go to Environment =>Flows =>Integrated Tools.

  2. For HDL Synthesis, push "Select" and choose Xilinx Webpack XST 9.1.

  3. For Implementation, push "Select" and choose Xilinx Webpack 9.1.

  4. For Family, choose the family. For example, selecting "Xilinx 9x Virtex5" sets the default family as Virtex 5. Selecting "Xilinx 9x Spartan3" sets the default family as Spartan 3.

  5. Push "OK" to save changes.

Option 2: Xilinx Environment (Home)

GUI Environment: Xilinx ISE Webpack 13.4
VHDL Simulator: ISim
Synthesis: Xilinx ISE Webpack XST 13.4
Implementation: Xilinx ISE Webpack 13.4

How to set up Xilinx Environment (Home)

This may take a few hours depending on your internet connection speed.

  1. Download and install Xilinx Webpack 13.4

    1. Go to the Xilinx Webpack and select 32/64bit windows.

    2. Create an account with Xilinx, then log back in.

    3. Proceed forward and select "ISE Webpack" and click the arrow button in the "Download" column in the box to the right.

    4. Once installed, you will need to follow Xilinx's guideline on obtaining license.

  2. When you open a new project in Xilinx ISE Webpack for the first time, initialize the environment to point to the correct tools.
    1. Go to File =>New Project. Create a project name and push "Next."

    2. For Product Category, choose "All."

    3. For Family, choose the family. For example, "Virtex5" or "Spartan3."

    4. For Synthesis tool, choose "XST (VHDL/Verilog)."

    5. For Simulator, choose "ISim (VHDL/Verilog)."

    6. For Preferred Language, choose "VHDL."

    7. Push "Next" and choose the rest of your options (by default, continue to push "Next" without making changes) until you push "Finish"

Option 3: Altera Environment (Home)

GUI/Environment: Altera Quartus II Web Edition 11.1
VHDL Simulator: ModelSim-Altera Starter Edition 10.0c SP1
Synthesis: Altera Quartus II
Web Edition Integrated Synthesis (QIS) 11.1
Implementation:
Altera Quartus II Web Edition Integrated Synthesis (QIS) 11.1, Fitter


How to set up Altera Environment (Home)

  1. Download and Install Altera Quartus II Web Edition 11.1
    1. Go to Altera Website and Create an account, then login into your account.

    2. Go to the Download Centre, download Altera Quartus II Web Edition 11.1 from this link.
    3. No License File is required to use Altera Quartus II Web Edition.

  1. Download and Install Modelsim-Altera Starter Edition 11.0
    1. Once logged in, Go to Modelsim-Altera Starter Edition

    2. Double Click the downloaded executable file to install and follow the instructions step by step.
    3. No License File is required to use Modelsim-Altera Starter Edition with Altera Quartus 11 Web Edition 11.1

  2. When you open a new project in Quartus II Web Edition, initialize the environment to point to the correct tools.
    1. Go to File..."New Project Wizard" and push "Next."

    2. For the Working Directory of the Project, choose Directory Name of your choice.

    3. Choose a "Name of the Project" and enter "Name of the Top-Level Design Entity" and Push "Next".

    4. In the next Window, Specify all existing files (If you have any),  select "Add All" and Push "Next".

    5. For Family, choose the family. For example, "Cyclone II" or "Stratix III" and Push "Next".

    6. Under EDA Tools, enter "Modelsim-Altera" for "Simulation" and select "Next".

    7. Push "Next" and choose the rest of your options (by default, continue to push "Next" without making changes) until you push "Finish."

    8. Once you have the complete VHDL source files for your design, Select "Compile Design" under "Task" to perform "Analysis & Synthesis" followed by "Fitter (Place & Route)". 

    9. Follow Steps "j" to "x", If you intend to perform RTL or Behavioral Simulation using Modelsim-Altera.

    10. Inside Quartus II Web Edition, Select the menu "Tools => Options => EDA Tool Options".
    11. For Modelsim-Altera, browse to the folder containing file "Modelsim.ini", usually located in the folder "~\modelsim_ae\win32aloem" and Push "Ok".

    12. Inside Quartus II Web Edition, Select the menu "Assignments => Settings => EDA Tool Synthesis => Simulation"
    13. Select "Modelsim-Altera" as the "Tool Name".

    14. Check the box for "Run gate-level simulation automatically after compilation", if you intend to perform this step automatically after compilation.
    15. Select "VHDL" as the "Format for Output Netlist"

    16. Select "simulation/modelsim" as the "Output Directory".

    17. Under NativeLink Settings, Choose "Compile test bench". Then click on "Test Benches".
    18. A new window appears, select "New".

    19. Another window appears. Enter the "Test bench Name".
    20. Enter the "Top-Level Module in Test Bench". Check the box "Use test bench to perform VHDL timing simulation".

    21. Enter the "Design instance name in test bench". It is the "Name of the Instance" for Top-Level design under test.
    22. Enter the simulation period. Add the testbench file and push "OK".

    23. Inside Quartus II Web Edition, Select the menu Tools => Run EDA Simulation Tool.
    24. Select the type of simulation you want to run.