ECE 699

Software/Hardware Codesign
Spring 2015



Time and location: Thursday, 7:20-10:00 PM, Aquia Building, room 219
Instructor: Kris Gaj
Email: kgaj (at) gmu.edu
Office hours: Monday 3:00-4:00 PM, Wednesday 3:00-4:00 PM, Thursday 6:00-7:00 PM, and by appointment
Co-Instructor: Malik Umar Sharif
Email: malik.umar.sharif (at) gmail.com
Office hours: Monday 12:00-1:00 PM, Wednesday 4:00-5:00 PM, Thursday 5:00-7:00 PM, and by appointment
Prerequisites: ECE 511 and ECE 545, or equivalent; knowledge of C and VHDL at the intermediate level or beyond
Syllabus: link


Required Textbooks:

L.H. Crockett, R.A. Elliot, M.A. Enderwitz, and R.W. Stewart, The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC, University of Strathlyde, Glasgow, UK, PDF copy available for free at http://www.zynqbook.com.

L.H. Crockett, R.A. Elliot, M.A. Enderwitz, and R.W. Stewart, The Zynq Book Tutorials, University of Strathlyde, Glasgow, UK, available for free at http://www.zynqbook.com/downloads.php.


Supplementary Textbooks:

P.R. Schaumont, A Practical Introduction to Hardware/Software Codesign, 2nd Ed, Springer, 2012, available for free for GMU students at Springer Link, http://link.springer.com.mutex.gmu.edu.

P.P. Chu, Embedded SoPC Design with Nios II Processor and VHDL Examples, 1st Ed., Wiley, 2011.


Software:

Development Board:

Course Outline (subject to possible modifications):

  1.    Objectives, Scope, and Organization. Introduction to ZYNQ.  01/22/2015
  2.    ZYNQ Design Flow. Class Exercise 1: First Design on ZYNQ.  01/29/2015
  3.    General Purpose Input Output, GPIO   02/05/2015
  4.    Interrupts. AXI GPIO and AXI Timer. Class Exercise 2: Next Steps in Zynq SoC Design.  02/12/2015
  5.    AXI Interfacing. IP Creation. Class Exercise 3: Creating IP in HDL.  02/19/2015
  6.    Using DMA & AXI4-Stream. Class Exercise 4: Using DMA and AXI4-Stream for communication with a hardware accelerator.   02/26/2015
  7.    Efficient Communication Between Hardware Accelerators and PS.   03/19/2015
  8.    Profiling Tools. Logic Analyzer.  03/26/2015
  9.    Midterm Exam.  04/02/2015
10.    High-Level Synthesis – Part 1.  04/09/2015
11.    High-Level Synthesis – Part 2. Class Exercise 5: Designing with Vivado High Level Synthesis. 04/16/2015
12.    HLS IPs. Class Exercise 6: Creating IP in Vivado HLS.  04/23/2015
13.    IP Reuse and Integration.  Class Exercise 7: Adventures with IP Integrator.  04/30/2015
14.    Operating Systems on ZYNQ.  05/06/2015
15.    Final Exam.  05/07/2015, 7:30-10:15pm

Lecture Slides

Lecture 10 - Linux on Zynq. [pdf]

Lecture 9 - High-Level Synthesis. Part 1. [ppt, pdf]

Lecture 8 - Integrated Logic Analyzer & Profiling. [ppt, pdf]

Lecture 7 - Efficient Communication Between Hardware Accelerators and PS. [ppt, pdf]

Lecture 6 - Using DMA & AXI4-Stream. [ppt, pdf]

Lecture 5 - AXI Interfacing. IP Creation. [ppt, pdf]

Lecture 4 - Interrupts. AXI GPIO and AXI Timer. [ppt, pdf]

Lecture 3 - General Purpose Input Output, GPIO [ppt, pdf]

Lecture 2 - ZYNQ Design Flow [ppt, pdf]

Lecture 1 - Introduction to ZYNQ [ppt, pdf]

Lecture 0 - Objectives, Scope, and Organization [ppt, pdf]

Posted gradually before a given lecture.
 

Class Exercise Tutorials

Tutorial 4: A Simple AXI-Stream Example Using HLS   example_c_code.c

Tutorial 3: Timing Analysis in Vivado 

Tutorial 2: Working with MIO LEDs and Pushbuttons    led_btns_ps.c

Tutorial 1: Getting the LEDs to flash
 

Homework Assignments

Homework Assignment 4 - Hardware Accelerator for Matrix Multiplication using Vivado HLS - due Sunday, 05/10, 11:59 PM

Homework Assignment 3 Revised and Extended - Hardware Accelerator for Matrix Multiplication - due Thursday, 04/08, 5:00 PM

Homework Assignment 2 - Using Button and Hardware Timer Interrupts - due Thursday, 02/19, 5:00 PM

Homework Assignment 1 - Using LEDs, Buttons, and Switches - due Thursday, 02/12, 5:00 PM

All exercises and assignments can be done individually or in a group of two students (group homework assignments will involve a larger number of tasks and/or more time-consuming tasks).

Class exercises that are not completed during the class time are expected to be finished at home.

Homework assignments are expected to be completed outside of the lecture time. Homework deliverables must be submitted on Blackboard by the specified deadline, and the required operation of the ZYNQ-based system and/or tools demonstrated to Umar during his office hours on Thursday, 5:00-7:00pm (or after the class the latest). If any of these two conditions is not met, the assignment will be considered one-week late, and penalized with 33% of points. No submissions will be accepted more than one week after its respective deadline. Honor code will be strictly enforced.

Grading Scheme


Class Exercises 5%
Homework Assignments* 45%
Midterms Exam 20%
Final Exam
30%
Class Activity up to 5%
of bonus points

  *up to 6 biweekly assignments; per individual requests these assignments may be replaced by a single project proposed by a given student or a group of two students  
 
 

Useful Resources


Tutorials

M.S. Sadri, ZYNQ Training

Xilinx, ZYNQ Video Tutorials

Xilinx, Vivado Video Tutorials

Xilinx, Vivado Design Suite Tutorial: Programming and Debugging

Xilinx, Vivado Design Suite Tutorial: High-Level Synthesis

S. Neuendorffer and F. Martinez-Vallina, Building Zynq Accelerators with Vivado High Level Synthesis, FPGA 2013 Tutorial

FPGA Tool Tutorials available on the page: Tutorials and Lab Manuals

Digilent, Embedded Linux Hands-on Tutorial for the ZYBO


Reference Manuals and User Guides

Xilinx, Zynq-7000 All Programmable SoC Technical Reference Manual

Digilent, ZYBO Reference Manual

Xilinx, Introduction to FPGA Design with Vivado High-Level Synthesis

Xilinx, Vivado Design Suite User Guide: High-Level Synthesis


Journals

Xcell Journal

Electronic Engineering Journal: FPGA and Programmable Logic Design


C Resources

Top 10 C Language resources that will turn you into a better programmer

C Programming Tutorial

C-Programming Resources


VHDL Resources

VHDL Instructions: Templates & Examples

Frequently Asked Questions about VHDL from comp.lang.vhdl

OpenCores Coding Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy

vhdl.org - HDL Resources of EDA Industry Working Groups


Related course web pages

ECE 511: Fall 2014

ECE 545: Fall 2014

ECE 645: Spring 2014

ECE 448: Spring 2014


Exams

Spring 2015 Midterm Exam, Part 1: Concepts:  text  solutions