Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design
Chapter 1, Numbers and Arithmetic
Chapter 2, Representing Signed Numbers
Problem 1: 4 points, submit on paper
Problem 2: 4 points, submit using WebCT
This problem is a FPGA tool flow problem. Implement the min-max-average circuit given in Hands-On Session 3 of the Fall 2007 ECE 545 class. Use the source code as is. You do not need to make any VHDL design changes:For this design:
perform pre-synthesis functional simulation
perform synthesis for Spartan 3
perform post-synthesis simulation if using Aldec (post-translate simulation if using Xilinx/Modelsim)
perform implementation targeting the smallest device of the Xilinx Spartan 3 family and optimized for minimum area
perform post-place-and-route timing simulation
perform static timing analysis
Submit the following files using WebCT. Do not submit more files or directories, only the ones listed below:
summary of resource utilization after place and route in a text file called summary.txt synthesis report full implementation report(s) static timing analysis report waveforms from timing simulation before synthesis (in .awf format for Active HDL or .wlf format for ModelSim) waveforms from timing simulation post synthesis (in .awf format for Active HDL) or post-translate (in .wlf format for ModelSim) waveforms from timing simulation post place-and-route (in .awf format for Active HDL or .wlf format for ModelSim)
In this file include: FPGA device used, number of slices (after place and route), minimum clock period (after place and route), maximum clock frequency (after place and route)