Project 2

 

Phase 1: Project Option and Specification Due: Monday, March 17, 12:00 noon

The choices for Project 2 are as follows. Each involves the FPGA implementation of a complex mathematical function. The first three are cryptography related and second three are digital signal processing related. The options are:
  1. Trial division sieve: Tambe, Shah, Brar
  2. Elliptic curve method of factoring: Yalla, Dharia, Velegalati
  3. RSA encryption & decryption with word-based Montgomery multipliers: Zumbrook, Peddi, Salman
  4. Iterative and pipeline CORDIC (coordinate rotation digital computer) processors: Nham, Anderson, Zia
  5. Finite impulse response filter architectures for FPGA implementations: Sharifi (alone), Thorpe (alone), Adam (alone)
  6. Direct digital frequency synthesis: Chaney (alone), Bhat (alone), Roeder (alone)
More details can be found here:
Project Options

What to turn in: Email Dr. Hwang by Monday, March 17, 12:00 noon, with: Phase 2: Project Reading and Specification (5 points) Due: Thursday, April 3, 12:00 noon via WebCT

In this phase of the project, you will perform background reading on your topic and will submit a brief (1-4 pages or so) report on the progress of your project. This report will include:
  1. PROJECT OUTCOME: Write a brief paragraph letting me know what your project outcome will be. For example, "The outcome of this project will be the FPGA implementation of a 256-bit radix-4 Booth multiplier. We will implement both sequential and full tree architectures of the multiplier. The implementations will be coded in VHDL and implemented on a Xilinx Spartan 3 FPGA. We will use the following architectural optimizations: 1) we will implement a carry-save adder tree, 2) we will ...."

  2. REFERENCES: List references of the papers you have read. You can see my publications page to see how you should format your references. For most of you I will give you some papers in PDF format.

  3. SUMMARY: For each paper you have read, write a brief summary (one paragraph) of the important parts of the paper.

  4. PROJECT PLAN: List the plan that you plan to proceed until the end of the semester. This can be in bullet point format or paragraph format. For example, "The project plan is as follows: 1) We will try to understand paper [1] in detail mathematically 2) We will then try to code a small part of the Booth multiplier according to paper [1]. In particular, we will code the partial product generator. 3) After we code...."

  5. OPEN ISSUES/PROBLEMS/QUESTIONS: Here list any open issues you may have going forward, any potential problem areas, and any questions you may have going forward.
Here are some papers you should read located in the zip files below:
  1. Trial division sieve: Your project outcome should be an FPGA implementation of a trial division circuit for 256-512 bit numbers. PAPERS

  2. Elliptic curve method of factoring: Your project outcome should be an FPGA implementation of the Elliptic Curve Method of factoring for 198-bit numbers using Meulenaer's architecture without DSP48 blocks. PAPERS

  3. RSA encryption & decryption with word-based Montgomery multipliers: Your project outcome should be an RSA encryption & decryption circuit with word-based Montgomery multipliers, which supports 1024-2048 bit numbers (using a parametrizable word size, baseline 16 bits). You will implement both the Huang/Gaj and Harris architectures. PAPERS

  4. Iterative and pipeline CORDIC (coordinate rotation digital computer) processors: Your project outcome should be an FPGA implementations of an iterative and a pipelined (unrolled) CORDIC processor. Each processor should be able to implement both vectoring and rotation modes with 16-bit data. PAPERS

  5. Finite impulse response filter architectures for FPGA implementations: Your project outcome should be a 16-bit input 256-tap FIR filter using Duhamel's divide by 2, 4, and 8 architectures, using different pipelining techniques to compare the best design in terms of throughput/area. You will each work separately on this project. PAPERS

  6. Direct digital frequency synthesis: Your project outcome should be an FPGA implementation of a DDFS circuit based on the architectures of Nicholas (Chaney), Bellaouar (Bhat), or Madisetti (Roeder) with a 32-bit accumulator and 12-bit output. PAPERS
Phase 3: Datapath Block Diagram and Controller, Test Plan (10 points) Due: Tuesday, April 15, 7:20 pm via WebCT

In this phase of the project, you will submit a rough draft of a datapath block diagram, controller ASM, and high-level interface diagram, as well as a test plan. Thus, you will turn in a brief document which includes:
  1. HIGH-LEVEL INTERFACE DIAGRAM: Please either draw this using a computer program or hand-draw it clearly and scan it in. You do not need to show the connections between datapath and controller; I am mainly interested to see the top-level entity input and output ports. Make sure to note which, if any, ports are generic. Please also create a chart or table briefly explaning each input and output of the circuit.

  2. DATAPATH (first draft): Please either draw this using a computer program or hand-draw it clearly and scan it in.

  3. CONTROLLER ASM (first draft): Please either draw this using a computer program or hand-draw it clearly and scan it in. If you do not want to use the ASM technique to build a controller, explain with diagrams exactly how your controller will work.

  4. TEST PLAN: Please indicate how you plan to make sure your circuit operates correctly. For example, test vectors can be generated in C, Matlab, VHDL, etc.

  5. OPEN ISSUES/PROBLEMS/QUESTIONS: Here list any open issues you may have going forward, any potential problem areas, and any questions you may have going forward.

Phase 4: Presentation (15 points) Due: Tuesday, April 29, 7:20 pm - 10:30 pm

In this phase of the project, you will present your project results. Your presentation should be approximately 25 minutes (+5 minutes for questions) for groups, and 13 minutes (+2 minutes for question) for individual projects. The talk should be tutorial in nature such that students with no background in your subject can understand more about the subject. The format of your talk should roughly be the following, as a suggestion. See the presentation order in the following PDF.
  1. INTRODUCTION: Introduce your specific arithmetic function, give some motivation about why it is important or where it is used. Include any explanations of mathematical formulas or deriviations that are used in your function.

  2. SPECIFICATION: Explain what you were supposed to design. You can show your high-level interface diagram here.

  3. ARCHITECTURE DISCUSSION: Explain how the design works, discuss your architecture and any decisions/optimizations you made. This should be a significant part of the presentation. You can show your block diagrams here.

  4. RESULTS AND ISSUES: Discuss your FPGA implementation results and any issues/problems you encountered. If you have not finished your design, indicate how far you are ("we have completed blocks A, B, C, working on block D") with implementation and testing. Discuss your test plan.

  5. CONCLUSIONS

Phase 5: Final Submission and Final Report (40 points) Due: Tuesday, May 6, 11:59 pm via WebCT

In this phase of the project, you will submit your final design files and your final report. You should submit via WebCT the following:

FINAL DESIGN FILES: Submit multiple sets of files in separate folders if you have multiple designs.
  1. All synthesizable VHDL source codes
  2. All testbenches used to verify the operation of the entire circuit and its components, and the corresponding input files containing test vectors, and output files containing results
  3. All code that is not in VHDL (i.e. C code, Matlab code) which you used to design, debug, or test your circuit, with any associated files they generate.
  4. Timing waveforms demonstrating the correct operation of the entire circuit and its components. Turn in: pre-synthesis waveform file (indicate file name clearly), post-synthesis or post-translate waveform file (indicate file name clearly), post-place-and-route waveform file (indicate file name clearly)
  5. Synthesis report
  6. Implementation report(s)
  7. Static timing analysis report
FINAL REPORT: The report can re-use material from Phases 2, 3, and 4, as well as add new material and results to make the report cohesive and readable. The report should be a PDF or Word Document.

  1. INFORMATION: Title of your project, names and emails of all group members.

  2. INTRODUCTION: Introduce your specific arithmetic function, give some motivation about why it is important or where it is used. Include any explanations of mathematical formulas or deriviations that are used in your function.

  3. SPECIFICATION: Briefly explain what you were supposed to design.

  4. HIGH-LEVEL INTERFACE DIAGRAM: Embed this diagram within your Word document or PDF, also create a table showing input and output ports of the top-level entity and discuss the ports. In the table, be sure to indicate the port bit widths and whether the ports are inputs or outputs. Show the connections and signals between datapath and controller.

  5. RELAVENT BLOCK DIAGRAMS: Embed the datapath block diagram and any relavent sub-block diagrams with a brief explanation of each block diagram.

  6. CONTROLLER DISCUSSION: Either embed the controller ASM (with a brief description) or describe in words the operation and function of the controller.

  7. TEST PLAN AND VERIFICATION: Describe your test plan and discuss how well your circuit performed against the chosen test vectors.

  8. IMPLEMENTATION RESULTS AND CRITICAL PATH IDENTIFICIATION: Show your results in tabular format. The table should include information post-place and route and must at least show: device used, slices, throughput, throughput/area, clock frequency, and latency in cycles and seconds, plus any additional design-specific information. Discuss your results. Discuss where the critical path in your design is, either in graphical or text format. Discuss any optimizations you made to your design.

  9. FEATURES: Discuss additional features of your design, particularly scalability (i.e. capability to use one generic code for an arbitrary operand size), ease of coding (i.e. number of lines of code, ease of determining a pattern of signals and interconnects), and testability (i.e. ease of determining the most critical path in the circuit and values of the corresponding test vectors).

  10. PROBLEMS OR ISSUES: Discuss any problems or unsolved issues you encountered with the design, testing, implementation, etc. of the project.

  11. CONCLUSIONS: Brief conclusion about the project and your results.

  12. REFERENCES: List the paper references you used. This can be the same list as Phase 2.