Exploiting STT-NV Technology for Reconfigurable, High Performance,
Low Power, and Low Temperature Functional Unit Design
Low-Current Probabilistic Writes for Power-Efficient MRAM Caches
Resistive Computation: A Critique
VAWOM: Temperature and Process Variation Aware WearOut
Management in 3D Multicore Architectures
Heterogeneous Memory Management for 3D-DRAM and External DRAM
with QoS
Managing Distributed UPS Energy for Effective Power Capping in Data
Centers
Dynamically Heterogeneous Cores through 3D Resource Pooling.
Variation Trained Drowsy Cache (VTD-Cache): A History Trained
Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
Hot Peripheral Thermal Management to Mitigate Cache Temperature  
Variation.
MZZ-HVS: Multi Modes Zig-Zag Horizontal and Vertical Sleep Transistor
Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits
Reducing Power in All Major CAM and SRAM Based Processor Units via
Centralized, Dynamic Resource Size Management
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced
Process Variation
FFT-Cache: A Flexible Fault-Tolerant Cache Architecture for Ultra Low  
Voltage Operation
Reliability-Aware Placement in SRAM-based FPGA for Voltage Scaling
Realization in the Presence of Process Variations
RELOCATE: Register File Local Access Pattern Redistribution
Mechanism for Power and Thermal Management in Out-of-Order
Embedded Processor
Exploiting Power Budgeting in Thermal-Aware Dynamic Placement for
Reconfigurable Systems
E < MC^2 : Less Energy through Multi-Copy Cache
Process Variation Aware Cache for Aggressive Voltage-Frequency   
Scaling
Fault Tolerant Cache Architecture for Sub 500mv Operation
Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in
Embedded Processors
Dynamic Register File Resizing and Frequency Scaling to Improve
Embedded Processor Performance and Energy-Delay Efficiency
Adaptive Techniques for Leakage Power Management in L2 Cache
Peripheral Circuits
Improving Performance and Reducing Energy-Delay with Adaptive
Resource Resizing for Out-Of-Order Embedded Processors

Houman Homayoun
Assistant Professor

Department of Electrical and Computer Engineering
Department of Computer Science (Courtesy Appointment)
George Mason University
Office: 3223, Engineering Building
Email:
hhomayou@gmu.edu
Phone: (703) 993-5430

Research Lab:
GOAL: Green Computing & Heterogeneous Architecture Lab


PhD positions are available for Fall 2015. Also several Master thesis
positions are available. The topics are Big Data Computing, Heterogeneous
Architecture Design, Enhancing Security against reverse-engineering. The
candidate need to have background in one of the following areas:
Computer Architecture, Machine Learning and Data Mining, Logic
Synthesis, FPGA, Parallel Programming, Real-time and Embedded Systems.
Please email me a copy of your CV if you are interested.
____________________________________________________________
Biographical Sketch

Houman Homayoun is an Assistant Professor of the Department of Electrical
and Computer Engineering at George Mason University. He also holds a joint
appointment with the Department of Computer Science.
Prior to joining George Mason University, He spent two years at the University
of California, San Diego, as National Science Foundation
Computing
Innovation
(CI) Fellow awarded by the Computing Research Association (CRA)
and the Computing Community Consortium (CCC).
Houman research is on power-temperature and reliability-aware memory and
processor design optimizations and spans the areas of computer architecture,
embedded systems, circuit design, and VLSI-CAD, where he has published
more than 30 technical papers on the subject, including some of the earliest
work in the field to address the importance of cross-layer power and
temperature optimization in memory peripheral circuits. He is currently leading
a number of research projects, including the design of next generation 3D
heterogeneous multicores, low power hybrid SRAM-NVM memory hierarchy
design, domain-specific acceleration, and power management in data centers.
Houman was a recipient of the four-year University of California, Irvine
Computer Science Department chair fellowship. He received his PhD degree
from the Department of Computer Science at the University of California, Irvine
in 2010, an MS degree in computer engineering in 2005 from University of
Victoria, Canada and his BS degree in electrical engineering in 2003 from
Sharif University of technology.
__________________________________________________________________
Research Interest

  • Green Computing, Heterogeneous Computing.
  • Heterogeneous Architecture Design.
  • Heterogeneous Architecture Mapping and Programming.
  • Big Data Computing.
  • 3D Integration and Design.
  • Hardware Security
  • Low Power and Thermal Aware Design.
  • DRAM Memory Management.
  • Emerging Memory Technologies (non-volatile STTRAM, PCM, and volatile HMC).
  • Performance Characterization in computing intensive application.
  • Energy efficiency and power management in enterprise datacenter.
____________________________________________________________
Honors & Awards
2013
2013
2010

2010

2006

2010
2009

2008

2006
2001

____________________________________________________________
Selected Publications
[ISLPED-2014]

[DAC-2014]
[ICCD-2014]

[GLSVLSI-2014]

[DATE 2014]

[ICCD 2013]
[CAL-2013]
[DAC 2013]

[ASP-DAC 2013]

[ISCA 2012]

[HPCA 2012]                
[TVLSI 2012]                

[ISQED 2012]             

[TVLSI 2011]              

[TVLSI 2011]           

[TVLSI 2011]             

[CASES 2011]          

[CODES-ISSS 2011]   

[HiPEAC 2010]          


[ISLPED 2010]      

[CASES 2010]            
[DATE 2009]              

[CASES 2009]             
[CASES 2008]             

[DAC 2008]                 

[ICCD 2008]             

[LCTES 2008]            


____________________________________________________________
Service

Technical Program Committee
IEEE/ACM Design Automation Conference (DAC 2015)
ACM Great Lakes Symposium on VLSI, (GLSVLSI 2015).
IEEE International Conference on Computer Design, (ICCD 2014).
IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI-2014)
International Green Computing Conference (IGCC-2014, 2013)
IEEE International Symposium on Quality Electronic Design (ISQED-2014, 2013, 2012, 2011)
IEEE International Symposium on Low Power Electronics Design (ISLPED-2012)
ACM International Conference on Computing Frontiers (CF-2011)
IEEE International Conference on Computer Systems and Applications (AICCSA-2011)

Special Session Organizer
A Uniform Approach to Heterogeneity, Design Automation Conference DAC 2014.

Conference Program Track Co-Chair
International Symposium on Quality Electronic Design, (ISQED 2014), System-level Design and
Methodologies (SDM)

Conference Web Chair
International Symposium on Performance Analysis of Systems and Software, ISPASS 2015.

Program Session Chair/Co-Chair
IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI-2014)
IEEE International Symposium on Quality Electronic Design (ISQED 2014, 2013)
International Symposium on Low Power Electronics and Design (ISLPED-2012)
IEEE International Conference on Computer Design (ICCD-2008)

External Reviewer of Conference Papers
International Symposium on Computer Architecture (ISCA)
International Symposium on High-Performance Computer Architecture (HPCA)
Design, Automation & Test in Europe (DATE)                                                  
International Conference on Parallel Architectures and Compilation Techniques (PACT)
International Conference on Supercomputing (ICS)
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
(CASES)
The ACM International Conference on Computing Frontiers (CF)
International Symposium on Computer Architecture and High Performance Computing (SBAC-
PAD)
IEEE International Symposium on Low Power Electronics Design (ISLPED)

External Reviewer of Journal Papers
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD)
The International Journal of Parallel Programming (IJPP)
The IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)
The IEEE Transactions on Computers (TC)


  • October, Serving on DAC 2015 Embedded
    Systems Track TPC.


  • July, Paper on Phase Change Material
    Modeling for Temperature Management
    accepted in ICCD 2014.

  • June, Invited paper on Enabling Dynamic
    Heterogeneity Through Core on Core
    Stacking in DAC 2014 .

  • June, Paper on Hybrid STT-RAM Cache
    accepted in IGCC 2014.

  • April, Paper on Mapping Biomedical
    Applications to Many-core accelerators
    accepted in ISLPED 2014.

  • January, Organizing a special session on
    Heterogeneous Architectures,
    Accelerators, Tools, and Workloads in DAC
    2014 Conference.

  • November, Paper on Non-volatile Logic
    Accepted at DATE conference.


  • October, Paper on Probabilistic Write for
    STT-RAMs presented at ICCD conference.



  • June, Paper on Resistive Computation: A
    Critique accepted at computer architecture
    letter.

  • June, Tutorial on Dynamic Heterogeneous
    Architecture will be presented at DAC 2013.

  • May, Keynote talk on Future of
    Heterogeneous Architecture at United
    States Patent and Trademark Office
    (USPTO).

  • May, Paper on Reliability in NUCA cache
    accepted at IGCC 2013.

  • March, Invited talk at Virgina Tech Center
    for Embedded Systems for Critical
    Applications (CESCA).

  • February, Paper on 3D multicore lifetime
    reliability accepted at DAC 2013.

  • September, paper on Heterogeneous 3D
    DRAM accepted at ASP-DAC 2013.


  • February, Tutorial on System-Level
    Exploration of Power, Temperature, and
    Performance accepted at DAC 2012.

  • December, Serving on the TPC of ISLPED
    2012.

  • November, Paper on "3D Heterogeneous
    Cores" Accepted at HPCA 2012.

  • November, Paper on "Inquisitive Defect
    Cache" appeared in TVLSI.

  • November, Paper on "MZZ-HVS
    peripherals" appeared in TVLSI.

  • November, Paper on "Centralized Power
    Management" appeared in TVLSI.

  • November, Paper on "Hot Peripheral
    Thermal Management" Accepted at ISQED
    2012.

  • November, Paper on "History & Variation
    Trained Cache" Accepted at ISQED 2012.

  • November, Invited talk on "Flexible Fault-
    Tolerant Cache Architecture" at 2011 SOC
    Conference


  • October, Paper on "FFT-Cache" appeared
    in CASES 2011

  • October, Paper on "Reliability-Aware
    Placement in SRAM-based FPGA"
    appeared in CODES-ISSS 2011


  •  December, Serving on the TPC of 2011
    IEEE-ISQED


  •  November, talk on "multiple sleep modes
    design" at Arizona State University

  •  November, Invited talk on "resource
    adaptation for power management" at 2010
    SOC Conference

  •  November, Paper on "multi copy cache
    architecture for reliability" appeared in
    CASES 2010


  •  September, paper on "multiple sleep
    mode design" accepted in TVLSI
Energy-efficient mapping of biomedical applications on domain-specific
accelerator under process variation
Enabling Dynamic Heterogeneity Through Core on Core Stacking
Modeling and Analysis of Phase Change Materials for Efficient Thermal
Management
A Parallel and Reconfigurable Architecture for Efficient OMP Compressive
Sensing Reconstruction
Exploiting STT-NV Technology for Reconfigurable, High Performance,
Low Power, and Low Temperature Functional Unit Design
Low-Current Probabilistic Writes for Power-Efficient MRAM Caches
Resistive Computation: A Critique
VAWOM: Temperature and Process Variation Aware WearOut
Management in 3D Multicore Architectures
Heterogeneous Memory Management for 3D-DRAM and External DRAM
with QoS
Managing Distributed UPS Energy for Effective Power Capping in Data
Centers
Dynamically Heterogeneous Cores through 3D Resource Pooling.
Variation Trained Drowsy Cache (VTD-Cache): A History Trained
Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
Hot Peripheral Thermal Management to Mitigate Cache Temperature  
Variation.
MZZ-HVS: Multi Modes Zig-Zag Horizontal and Vertical Sleep Transistor
Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits
Reducing Power in All Major CAM and SRAM Based Processor Units via
Centralized, Dynamic Resource Size Management
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced
Process Variation
FFT-Cache: A Flexible Fault-Tolerant Cache Architecture for Ultra Low  
Voltage Operation
Reliability-Aware Placement in SRAM-based FPGA for Voltage Scaling
Realization in the Presence of Process Variations
RELOCATE: Register File Local Access Pattern Redistribution
Mechanism for Power and Thermal Management in Out-of-Order
Embedded Processor
Exploiting Power Budgeting in Thermal-Aware Dynamic Placement for
Reconfigurable Systems
E < MC^2 : Less Energy through Multi-Copy Cache
Process Variation Aware Cache for Aggressive Voltage-Frequency   
Scaling
Fault Tolerant Cache Architecture for Sub 500mv Operation
Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in
Embedded Processors
Dynamic Register File Resizing and Frequency Scaling to Improve
Embedded Processor Performance and Energy-Delay Efficiency
Adaptive Techniques for Leakage Power Management in L2 Cache
Peripheral Circuits
Improving Performance and Reducing Energy-Delay with Adaptive
Resource Resizing for Out-Of-Order Embedded Processors