library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity problem_tb is
end problem_tb;

architecture behavioral of problem_tb is		 

signal resetn: std_logic;
signal clk: std_logic := '1';
signal m: std_logic_vector(1 downto 0);
signal r: std_logic_vector(1 downto 0):="01";
signal s: std_logic;

begin	 
	reset_non_periodical: process 
	begin
		resetn <= '0';
		wait for 200 ns;
		resetn <= '1';
		wait;
	end process;	
	
	clk <= not clk after 100 ns;	

	m_non_periodical: process	
	begin
		m <= "00";
		wait for 100 ns;
		m <= "10";
		wait for 250 ns;
		m <= "00";
		wait for 150 ns;
		m <= "01";
		wait for 200 ns;
		m <= "10";
		wait for 200 ns;
		m <= "00";
		wait;
	end process;	 
	
	r_periodical: process	
	begin
		for i in 0 to 3 loop	 
			wait for 200 ns;
			r <= r + "01"; 
		end loop;
	end process;   
	
	s_periodical: process	
	begin
	 	s <= '0';
		wait for 200 ns;	 
		s <= '1';
		wait for 400 ns;
		s <= '0';
		wait for 200 ns;
	end process;

end behavioral;