Kris Gaj

Books and Proceedings

  1. C. Clavier and K. Gaj (Eds.), Cryptographic Hardware and Embedded Systems - CHES 2009, 11th International Workshop, Lausanne, Switzerland, September 6-9, 2009, Proceedings, Series: Lecture Notes in Computer Science, Subseries: Security and Cryptology, vol. 5747, Sep. 2009. ISBN: 978-3-642-04137-2.
     
  2. K. Gaj and P. Chodowiec, "FPGA and ASIC Implementations of AES," Chapter 10 in C.K. Koc (Ed.), Cryptographic Engineering, pp. 235-320, Springer, Dec. 2008. ISBN-10: 0387718168. ISBN-13: 978-0387718163.
     
  3. K. Gaj, The Enigma Cipher: Methods of Breaking, Transport and Communications Press, Warsaw, Poland, 1989 (in Polish).
     

Journal and Peer-Review Conference Publications

  1. M. Rogawski, K. Gaj, E. Homsirikamol, "A High-Speed Unified Hardware Architecture for 128 and 256-bit Security Levels of AES and the SHA-3 Candidate Grøstl,"  Microprocessors and Microsystems - Embedded Hardware Design, vol. 37, no. 6-7, Aug.-Oct. 2013, pp. 572-582.

  2. B. Habib, K. Gaj and J.-P. Kaps, "FPGA PUF based on Programmable LUT Delays," in 16th Euromicro Conference on Digital System Design - DSD 2013, Santander, Spain, Sep. 2013, pp. 697-704 (accepted version + slides).

  3. B. Brewster, E. Homsirikamol, R. Velegalati, K. Gaj, "Option Space Exploration Using Distributed Computing for Efficient Benchmarking of FPGA Cryptographic Modules," in 2012 International Conference on Field Programmable Technology - FPT 2012, Seoul, Korea, Dec. 2012.

  4. S. Paul, E. Homsirikamol, and K. Gaj, "A Novel Permutation-based Hash Mode of Operation FP and The Hash Function SAMOSA," in 13th International Conference on Cryptology in India - Indocrypt 2012, Chenai, India, Dec. 2012.

  5. M. Rogawski and K. Gaj, "A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl", in 15th Euromicro Conference on Digital System Design - DSD 2012, Cesme, Izmir, Turkey, Sep. 2012 (paper + slides).

  6. R. Shahid, U. Sharif, M. Rogawski, and K. Gaj, "Use of Embedded FPGA Resources in Implementations of 14 Round 2 SHA-3 Candidates," in 2011 International Conference on Field Programmable Technology - FPT 2011, New Delhi, India, Dec. 2011. (slides + accepted version) © 2011 IEEE. See the IEEE Copyright Notice below.

  7. E. Homsirikamol, M. Rogawski, and K. Gaj, "Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs," in LNCS 6917, Cryptographic Hardware and Embedded Systems - CHES 2011, Nara, Japan, Sep. 28-Oct. 1, pp. 491-506. (paper + slides)

  8. M. Huang, K. Gaj, and T. El-Ghazawi, "New Hardware Architectures for Montgomery Modular Multiplication Algorithm," IEEE Transactions on Computers, vol. 60, no. 7, July 2011, pp. 923-936. (abstract + accepted version) © 2011 IEEE. See the IEEE Copyright Notice below.

  9. K. Gaj and R. Steinwandt, "Editorial: Hardware Architectures for Algebra, Cryptology, and Number Theory," Integration, the VLSI Journal, vol. 44, no. 4, Sep. 2011, pp. 257-258 (paper).

  10. K. Gaj, S. Kwon, P. Baier, P. Kohlbrenner, H. Le, M. Khaleeluddin, R. Bachimanchi, and M. Rogawski, "Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve," IEEE Transactions on Computers, vol. 59, no. 9, Sep. 2010, pp. 1264-1280. (abstract + accepted version) © 2010 IEEE. See the IEEE Copyright Notice below.

  11. K. Gaj, J.P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol, B.Y. Brewster, “ATHENa – Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware using FPGAs,” 20th International Conference on Field Programmable Logic and Applications, Milano, Italy, Aug. 31st - Sep. 2nd, 2010 (best paper FPL Community award) (slides + abstract + accepted version) © 2010 IEEE. See the IEEE Copyright Notice below.
     
  12. K. Gaj, E. Homsirikamol, and M. Rogawski, “Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs,” in LNCS 6225, Cryptographic Hardware and Embedded Systems - CHES 2010, Santa Barbara, CA, USA, Aug. 2010, pp. 264-278 (paper + slides).
     
  13. C. Shu, S. Kwon, and K. Gaj, "Reconfigurable Computing Approach for Tate Pairing Cryptosystems over Binary Fields", IEEE Transactions on Computers, vol. 58, no. 9, pp. 1221-1237, Sep. 2009. (abstract + accepted version) © 2009 IEEE. See the IEEE Copyright Notice below.
     
  14. R. Vaslin, G. Gogniat, J.-P. Diguet, R. Tessier, D. Unnikrishnan, and K. Gaj, "Memory security management for reconfigurable embedded systems," Proc. International Conference on Field Programmable Technology, FPT 2008, Taipei, pp. 153-160, Dec. 2008. (paper)
     
  15. P. Saha, E. El-Araby, M. Huang, M. Taher, S. Lopez-Buedo, T. El-Ghazawi, C. Shu, K. Gaj, A. Michalski, and D. Buell, "Portable Library Development for Reconfigurable Computing Systems: A Case Study", Elsevier Parallel Computing: Systems & Applications, vol. 34, issues 4+5, pp. 245-260, May 2008. ISSN: 0167-8191. (paper)
     
  16. M. Huang, K. Gaj, S. Kwon, and T. El-Ghazawi, "An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm," Proc. 11th International Workshop on Practice and Theory in Public Key Cryptography, PKC 2008, Barcelona, Spain, pp. 214-228, Mar. 2008. (paper + slides)

  17. T. El-Ghazawi, E. El-Araby, M. Huang, K. Gaj, V. Kindratenko, D. Buell, "The Promise of High-Performance Reconfigurable Computing," Computer, vol. 41, no. 2, pp. 69-76, Feb. 2008. (paper)

  18. D. Hwang, M. Chaney, S. Karanam, N. Ton, and K. Gaj, "Comparison of FPGA-targeted hardware implementations of eSTREAM stream cipher candidates," Proc. State of the Art of Stream Ciphers Workshop, SASC 2008, Lausanne, Switzerland, pp. 151-162, Feb. 2008. (paper + slides)

  19. G. Southern, C. Mason, L. Chikkam, P. Baier, and K. Gaj, "FPGA Implementation of High Throughput Circuit for Trial Division by Small Primes," Proc. Special Purpose Hardware for Attacking Cryptographic Systems, SHARCS 2007, Vienna, Austria, Sep. 2007. (paper + slides)
     
  20. A. Abusharekh and K. Gaj, "Comparative Analysis of Software Libraries for Public Key Cryptography," Proc. Software Performance Enhancement for Encryption and Decryption, SPEED 2007, Amsterdam, the Netherlands, June 2007, pp. 3-19. (paper + slides)

  21. D. Buell, T. El-Ghazawi, K. Gaj, V. Kindratenko, "High-Performance Reconfigurable Computing: Guest Editors' Introduction," Computer Magazine, special issue, Mar. 2007. (paper)

  22. K. Gaj, G. Southern and R. Bachimanchi, "Comparison of Hardware Performance of Selected Phase 2 eSTREAM Candidates," Proc. SASC 2007: Stream Ciphers Revisited, ECRYPT eSTREAM workshop, Bochum, Germany, Jan. 31-Feb. 1, 2007. (paper + slides)

  23. C. Shu, S. Kwon, K. Gaj, "FPGA Accelerated Tate Pairing Based Cryptosystems over Binary Fields," Proc. IEEE 2005 Conference on Field Programmable Technology, FPT'06, Bangkok, Dec. 13-15, 2006. (paper + slides)

  24. K. Gaj, S. Kwon, P. Baier, P. Kohlbrenner, H. Le, M. Khaleeluddin, R. Bachimanchi, "Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware," CHES 2006, Cryptographic Hardware and Embedded Systems workshop, Yokohama, Japan, Oct 10-13, 2006. (paper + slides)

  25. K. Gaj, S. Kwon, P. Baier, P. Kohlbrenner, H. Le, M. Khaleeluddin, R. Bachimanchi, "Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware," Proc. Special Purpose Hardware for Attacking Cryptographic Systems, SHARCS 2006, Cologne, Germany, Apr. 3-4, 2006. (paper + slides)

  26. D. Misra and K. Gaj, "Face Recognition CAPTCHAs," Proc. Advanced International Conference on Telecommunications and International Conference on Internet and Web Applications and Services, AICT/ICIW 2006, 19-25 February 2006, Guadeloupe, French Caribbean (paper).
     
  27. E. El-Araby, M. Taher, K. Gaj, T. El-Ghazawi, D. Caliga, N. Alexandridis, "System-Level Parallelism and Concurrency Maximization in Reconfigurable Computing Applications,” International Journal of Embedded Systems (IJES), vol. 2, no.1/2, pp. 62-72, 2006. (paper)

  28. A. S. Zeineddini and K. Gaj, "Secure Partial Reconfiguration of FPGAs," Proc. IEEE 2005 Conference on Field Programmable Technology, FPT'05, Singapore, Dec. 11-14, 2005. (paper + slides)

  29. C. Zouridaki, M. Hejmo, B. L. Mark, R. K. Thomas, K. Gaj, "Analysis of Attacks and Defense Mechanisms for QoS Signaling," Proc. 4th International Workshop on Wireless Information Systems, WIS 2005, in conjunction with ICEIS 2005, Miami, USA, May 2005, pp. 61-70. (paper + slides)

  30. S. Bajracharya, D. Misra, K. Gaj, T. El-Ghazawi , "Reconfigurable Hardware Implementation of Mesh Routing in Number Field Sieve Factorization," Proc. Special Purpose Hardware for Attacking Cryptographic Systems, SHARCS 2005, Paris, France, Feb. 24-25, 2005, pp. 71-81. (paper + slides)

  31. H. Kurnio, H. Wang, J. Pieprzyk, K. Gaj, "Securing Multicast Groups in Ad Hoc Networks," LNCS 3309, Advanced Workshop on Content Computing, AWCC 2004, ZhenJiang, JiangSu, China, November 15-17, 2004, pp. 194-207. (paper + slides)

  32. S. Bajracharya, D. Misra, K. Gaj, T. El-Ghazawi, "Reconfigurable Hardware Implementation of Mesh Routing in Number Field Sieve Factorization," Proc. IEEE 2004 Conference on Field Programmable Technology, FPT 2004, Brisbane, Australia, Dec. 6-8, 2004, pp. 263-270. (paper + slides)

  33. T. El-Ghazawi, K. Gaj, N. Alexandridis, F. Vroman, N. Nguyen, J. R. Radzikowski, P. Samipagdi, and S. A. Suboh, "An Empirical Comparative Study of Job Management Systems," Concurrency: Practice and Experience, vol. 16, no. 13, Nov. 2004, pp. 1229-1246. (paper)

  34. S. Kwon, K. Gaj, C.-H. Kim, C.-P. Hong, "Efficient Linear Array for Multiplication in GF(2m) Using a Normal Basis for Elliptic Curve Cryptography," in LNCS 3156, Cryptographic Hardware and Embedded Systems - CHES 2004, Cambridge, MA, USA, Aug. 2004, pp. 76-91. (paper + slides)

  35. S. Bajracharya, C. Shu, K. Gaj, T. El-Ghazawi, "Implementation of Elliptic Curve Cryptosystems over GF(2n) in Optimal Normal Basis on a Reconfigurable Computer," 14th International Conference on Field Programmable Logic and Applications, FPL 2004, Antwerp, Belgium, Aug 30 - Sept 1, 2004, pp. 1001-1005. (paper + slides)

  36. C. Zouridaki, B. L. Mark, K. Gaj, R. K. Thomas, "Distributed CA-based PKI for Mobile Ad Hoc Networks Using Elliptic Curve Cryptography," LNCS 3093, Public Key Infrastructure, First European PKI Workshop: Research and Applications, EuroPKI 2004, Samos Island, Greece, June 25-26, 2004, pp. 232-245. (paper + slides)

  37. E. El-Araby, M. Taher, K. Gaj, T. El-Ghazawi, D. Caliga, and N. Alexandridis, “System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications”, Proc. Reconfigurable Architecture Workshop, RAW 2004, Santa Fe, New Mexico, USA, April, 2004 (paper + slides)
     
  38. R. Lien, T. Grembowski, K. Gaj, "A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512," LNCS 2964, RSA Conference 2004, Cryptographers' Track, CT-RSA 2004, San Francisco, CA, Feb. 2004, pp. 324-328. (paper + slides)

  39. P. Kohlbrenner and K. Gaj, "An Embedded True Random Number Generator for Field Programmable Gate Arrays," Proc. ACM/SIGDA Twelve International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, CA, Feb. 2004, pp. 71-78. (paper + slides)

  40. N. Nguyen, K. Gaj, D. Caliga, T. El-Ghazawi, "Implementation of Elliptic Curve Cryptosystems on a Reconfigurable Computer," Proc. IEEE International Conference on Field-Programmable Technology, FPT 2003, Tokyo, Japan, Dec. 2003, pp. 60-67. (paper + slides)

  41. P. Chodowiec and K. Gaj, "Very Compact FPGA Implementation of the AES Algorithm," in LNCS 2779, Cryptographic Hardware and Embedded Systems - CHES 2003, Cologne, Germany, Sep. 2003, pp. 319-333. (paper + slides)
     
  42. A. Michalski, K. Gaj, T. El-Ghazawi, "An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers," LNCS 2778, 13th International Conference on Field Programmable Logic and Applications, FPL 2003, Lisbon, Portugal, Sep. 2003, pp. 204-219. (paper + slides)
     
  43. P. Bellows, J. Flidr, L. Gharai, C. Perkins, P. Chodowiec, and K. Gaj, "IPsec-Protected Transport of HDTV over IP, LNCS 2778, 13th International Conference on Field Programmable Logic and Applications, FPL 2003, Lisbon, Portugal, Sep. 2003, pp. 869-879. (paper)
     
  44. K. Gaj and A. Orlowski, "Facts and Myths of Enigma: Breaking Stereotypes," LNCS 2656, Advances in Cryptology – EUROCRYPT 2003, Ed. E. Biham, International Conference on the Theory and Applications of Cryptographic Techniques, EUROCRYPT 2003, Warsaw, Poland, May 2003, pp. 106-122 (invited paper). (paper + slides)

  45. K. Gaj, T. El-Ghazawi, N. Alexandridis, J. R. Radzikowski, M. Taher, and F. Vroman, "Effective Utilization and Reconfiguration of Distributed Hardware Using Job Management Systems," Proc. Reconfigurable Architecture Workshop, RAW 2003, Apr. 2003. (paper + slides)
     
  46. O. D. Fidanci, D. Poznanovic, K. Gaj, T. El-Ghazawi, and N. Alexandridis, "Performance and Overhead in a Hybrid Reconfigurable Computer," Proc. Reconfigurable Architecture Workshop, RAW 2003, Apr. 2003. (paper + slides)

  47. T. Grembowski, R. Lien, K. Gaj, N. Nguyen, P. Bellows, J. Flidr, T. Lehman, B. Schott, "Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512," LNCS 2433, Information Security, Eds. G. I. Davida, Y. Frankel, 5th International Conference, ISC 2002, Sao Paulo, Brazil, Sep./Oct. 2002, pp. 75-89. (paper + slides)

  48. K. Gaj, T. El-Ghazawi, N. Alexandridis, F. Vroman, N. Nguyen, J. R. Radzikowski, P. Samipagdi, and S. A. Suboh, "Performance Evaluation of Selected Job Management Systems," Proc. Workshop on Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems, PMEO 2002, Fort Lauderdale, Florida, Apr. 2002. (paper + slides)

  49. P. Chodowiec, K. Gaj, P. Bellows, and B. Schott, "Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board," LNCS 2200, Information Security, Eds. G. I. Davida, Y. Frankel, 4th International Conference, ISC 2001, Malaga, Spain, Oct. 2001, pp. 220-234. (paper + slides)
     
  50. M. Taher, K. Gaj, T. El-Ghazawi, and N. Alexandridis, "Job Management System Extension To Support SLAAC-1V Reconfigurable Hardware," Proc. 2001 MAPLD International Conference, Laurel, Maryland, Sep. 2001. (paper + slides)

  51. A.V. Staicu, J. R. Radzikowski, K. Gaj, N. Alexandridis, and T. El-Ghazawi, "Effective Use of Networked Reconfigurable Resources," Proc. 2001 MAPLD International Conference, Laurel, Maryland, Sep. 2001. (paper + slides)

  52. K. Gaj and P. Chodowiec, "Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard using Field Programmable Gate Arrays," LNCS 2020, Progress in Cryptology - CT-RSA 2001, Ed. D. Naccache, RSA Conference 2001 - Cryptographers' Track, San Francisco, Apr. 2001, pp. 84-99. (paper + slides)

  53. P. Chodowiec, P. Khuon, and K. Gaj, "Fast Implementations of Secret-Key Block Ciphers Using Mixed Inner- and Outer-Round Pipelining," ACM/SIGDA Ninth International Symposium on Field Programmable Gate Arrays, Monterey, CA, Feb. 2001, pp. 94-102. (paper + slides)

  54. K. Gaj and P. Chodowiec, "Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware," Proc. 3rd Advanced Encryption Standard Conference, New York, April 2000, pp. 40-54. (paper + slides)

Technical Reports

  1. S. Paul, E. Homsirikamol, and K. Gaj, "A Novel Permutation-based Hash Mode of Operation FP and the Hash Function SAMOSA," Cryptology ePrint Archive: Report 2012/597, Oct. 2012 (report).

  2. K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, "Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs," Cryptology ePrint Archive: Report 2012/368, first version - June 2012, final version - October 2012 (report).

  3. M. Rogawski and K. Gaj, "Groestl Tweaks and Their Effect on FPGA Results," Cryptology ePrint Archive: Report 2011/635, Nov. 2011 (report).

  4. E. Homsirikamol, M. Rogawski, and K. Gaj, "Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs," Cryptology ePrint Archive: Report 2010/445, first version - Aug. 2010 (report).
     
  5. K. Gaj and P. Chodowiec, "Hardware performance of the AES finalists - survey and analysis of results," Technical Report, George Mason University, Sep. 2000. (report)
     
  6. P. Chodowiec and K. Gaj,  "Implementations of the Twofish Cipher Using FPGA Devices," Technical Report, George Mason University, July 1999. (report)
     
  7. T. El-Ghazawi, K. Gaj, N. Alexandridis, B. Schott, A. V Staicu, J. R. Radzikowski, N. Nguyen, S. A. Suboh, “Conceptual Comparative Study of Job Management Systems,” Technical Report, George Mason University, Feb. 2001. (report + appendix)
     
  8. T. El-Ghazawi, K. Gaj, N. Alexandridis, B. Schott, A. V Staicu, J. R. Radzikowski, N. Nguyen, J. Vongsaard, and S. Chauvin, P. Samipagdi and S. A. Suboh, “Experimental Comparative Study of Job Management Systems,” Technical Report, George Mason University, Jul. 2001. (report)
     

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