ECE 545
Digital System Design with VHDL

Fall 2010

Time and location:    Monday, 4:30-7:10 PM, Engineering Building, room 1109

Instructor:                  Kris Gaj  
Office hours:             Monday, 7:30-8:30 PM; Wednesday 6:00-7:00 PM
                                    The Engineering Building, room 3225

TA:                              Kishore Surapathi
Office hours:
            Monday, 7:30-9:30 PM; Tuesday 3:00-5:00 PM
                                    The Engineering Building, room 3224


Please submit all your homework and project reports using Blackboard by going to


Course Description

Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis and performance optimization. Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs. 

Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly recommended.


Required Textbooks

Pong P. ChuRTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006.


Supplementary Textbooks

Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Edition, McGraw-Hill, 2008.

Volnei A. Pedroni, Circuit Design with VHDL, The MIT Press, 2004.

Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998.

Peter J. Ashenden, The Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann Publishers, 2008.

Software Packages Used in This Class

  • Aldec Active HDL
  • Mentor Graphics ModelSim
  • ModelSim Xilinx Edition III
  • Synplicity Synplify Pro
  • Xilinx XST
  • Xilinx ISE
  • Xilinx WebPACK
  • Altera Quartus II

All software will be available in the Computer Engineering Lab, The Engineering Building, room 3208.
Selected software can be installed on your laptops and home workstations.


This year's project will involve implementing a selected cryptographic hash function competing in the contest for a new American hash standard SHA-3.
The list and specification of remaining SHA-3 candidates is available here. Each student will design, implement, and optimize one algorithm assign to him/her by the instructor. All implementations will be optimized using multiple criteria and implemented using multiple families of FPGAs from Xilinx and Altera. This project will support NIST in selection of a hash algorithm most suitable from the point of view of  hardware efficiency.

Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs,
by Ekawat Homsirikamol, Marcin Rogawski, and Kris Gaj, Cryptology ePrint Archive: Report 2010/445 - Revised October 10, 2010

Second Round 2 SHA-3 Candidates

SHA-3 Zoo - Hardware Implementations

Materials from the SHA-3 Project Review Meeting with NIST on November 9, 2010: NEW!!!

GMU SHA Core Interface and Hash Function Performance Metrics [PPT, PDF, PDF2] - NEW!!!

ATHENa Website

FPGA Embedded Resources

Project Phase 2 - due Sunday, November 21, 11:59 PM

Project Phase 3 - due Wednesday, December 1, 11:59 PM

mini-SHA example NEW!!!

Project Deliverables - due Thursday, December 16, 11:59 PM


Homework 1 - due Thursday, October 7, 11:59 PM

Homework 2 + test vectors + slides [PPT, PDF] - due Saturday, October 23, 11:59 PM

Homework 3 - due Sunday, November 7, 11:59 PM

Homework assignments will be posted gradually here, at least 6 days before a given assignment's due date.



Lecture 1 - Digital Logic Review [PPT, PDF, PDF6]

         Class Exercise 1        Class Exercise 2

Lecture 2 - Introduction to the Course Project [PDF, PDF6]

Lecture 3 - Introduction to VHDL for Synthesis [PPT, PDF, PDF6]

Lecture 4 - Simple Testbenches [PPT, PDF, PDF6]

Lecture 5 - Dataflow Modeling of Combinational Logic [PPT, PDF, PDF6]

Lecture 6 - Behavioral Modeling of Sequential-Circuit Building Blocks [PPT, PDF, PDF6] - updated on Tuesday, Oct. 5 (slides 33, 36, 43, 45)

Lecture 7 - Modeling of Circuits with a Regular Structure. Aliases, Attributes, Packages. Mixing Design Styles. [PPT, PDF, PDF6]

Lecture 8 - RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram.  [PPT, PDF, PDF2]

Lecture 9 - FPGA Devices & FPGA Device Flow. [PPT, PDF, PDF6]

Lecture 10 - Advanced Testbenches. [PPT, PDF, PDF6]

Lecture 11 - ATHENa & FPGA Embedded Resources. [PPT, PDF, PDF6] revised on Monday, Nov. 22, 8:00pm (slides 29, 44, 65)

Lecture 12 - Design of Controllers. Finite State Machines and Algorithmic State Machine (ASM) Charts. [PPT, PDF, PDF6]

Viewgraphs will be posted gradually here, at least one day before a given lecture.


Reference Material


VHDL Instructions: Templates & Examples

Frequently Asked Questions about VHDL from comp.lang.vhdlNEW!!!

OpenCores HDL Modeling Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy - HDL Resources of EDA Industry Working GroupsNEW!!!



The Detailed Instructions on How to Configure your FPGA Tools at School, and Install and Configure your FPGA Tools at Home (last updated 11/01/2010)

Xfig - Installation and Start-up Guide (last updated 09/25/2010)

Tutorial on Simulation using Aldec Active-HDL (last updated 09/20/2010)

Tutorial on FPGA Design Flow based on Aldec Active-HDL (last updated 10/31/2010

Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim (last updated 10/31/2010

Tutorial on Concurrent Version System based on CVS NT and Tortoise CVS (to be updated)

Past Course Web Pages

ECE 545:     Fall 2008 (with Dr. Hwang)   Fall 2009 (with Dr. Gaj)

ECE 448:     Spring 2010 (with Dr. Gaj)


Practice and Past Exams

Midterm Exam 2009 

Solutions to the Midterm Exam 2009: Task 1  Task 2  Task 3  Task 4

Midterm Exam 2009: Recommended Reading and Practice Problems

Practice Midterm Exam

Solutions to the Practice Midterm Exam

Midterm Exam 1 from Fall 2006

Midterm Exam 1 from Fall 2005

Midterm Exam 1 from Fall 2004


Midterm Exam 2 from Fall 2006

Midterm Exam 2 from Fall 2005

Midterm Exam 2 from Fall 2004