Time and
location:

Thursday, 7:2010:00 PM, Krug Hall, room
5

Instructor:


Email:

kgaj@gmu.edu

Office
hours:

Tuesday, Thursday 6:007:00 PM, and by
appointment
The Engineering Building, room 3225



TA:

Sanjay Deshpande

Office
hours:

Tuesday 6:007:00 PM, Wednesday
3:004:00 PM, and by appointment


The Engineering Building, room 3231

Email:

sdeshpan@masonlive.gmu.edu

Please submit all your homework and project
reports using MyMason
by going to http://mymasonportal.gmu.edu
Please
use Piazza
instead of email for asking questions related to
this class
Course Description
Introduces
the design of complex digital systems using hardware
description languages. Teaches design methodologies
which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code
for digital circuit design using dataflow,
structural, and behavioral coding styles. Introduces
VHDL simulation and verification, and FPGA
synthesis, placement, routing, timing analysis, and
performance optimization. Requires semesterlong
project devoted to the design of a complex digital
system implemented on FPGAs.
Prerequisites: Graduate
Standing.
No official course prerequisite is required, but an
undergraduate background in digital logic design is
strongly recommended.
Required Textbooks
Pong P. Chu, RTL Hardware Design Using VHDL:
Coding for Efficiency, Portability, and Scalability,
WileyIEEE Press, 2006.
Supplementary
Textbooks
Hubert
Kaeslin, Digital
Integrated
Circuit Design: From VLSI Architectures to CMOS
Fabrication, Cambridge University Press; 1st
Edition, 2008.
Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design,
3rd Edition, McGrawHill, 2008.
Volnei A.
Pedroni, Circuit
Design and Simulation with VHDL, 2nd
Edition, The MIT Press, 2010.
Sundar Rajan, Essential
VHDL: RTL Synthesis Done Right, S & G
Publishing, 1998.
Peter J. Ashenden,
The
Designer's Guide to VHDL, 3rd
Edition, Morgan Kaufmann Publishers, 2008.
Software Packages Used in This
Class
All software will be available in the
Computer Engineering Labs, The Engineering Building,
rooms 3208 and 3204.
Selected FREE software can be installed on your
laptops and home workstations.
Course Outline
(subject to possible modifications):
 Organization of the
Course. Introduction to FPGA Technology.
09/03/2015
 Project Background. 09/10/2015
 Digital Logic Refresher. 09/17/2015
 RTL
Design Methodology. 09/24/2015
 VHDL Basics. Simple Testbenches. 10/01/2015
 Block Diagrams. Modes of Operation of Block
Ciphers. 10/08/2015
 Advanced
Testbenches. 10/15/2015
 Dataflow Modeling in
VHDL. Dataflow Description of
CombinationalCircuit Building Blocks in VHDL. 10/22/2015
 Behavioral Modeling of
SequentialCircuit Building Blocks. Mixing Design Styles. Modeling
of Circuits with Regular Structure. 10/29/2015
 Midterm
Exam. 11/05/2015
 FPGA
Devices & FPGA Device Flow. Poor Design Practices. Measures of
the Circuit Performance. 11/12/2015
 Design
of Controllers  Finite State Machines and Algorithmic
State Machine (ASM) Charts. 11/19/2015
 Design of
Controllers  Alternative
Coding Styles.
Controllers
for Keccak_F and AES.
Project Deliverables.
12/03/2015
 Modeling
of Memories in
FPGAs.
Using
FPGA Embedded Resources. Timing
Analysis. ATHENa
 Automated Tool for Hardware
EvaluatioN.
12/10/2015
 Final Exam. 12/17/2015, 7:3010:15pm
Project Resources
This
year's project will involve implementing a selected
authenticated cipher competing in the CAESAR
contest. Each student will design, implement,
and optimize one algorithm assigned to him/her by
the instructor. All implementations will be
optimized using multiple criteria and implemented
using multiple families of FPGAs from Xilinx and
Altera. This project will support standardization
organizations, such as NIST, in selection of a new
authenticated encryption standard most suitable from
the point of view of hardware efficiency.
The
following websites contain useful resources for this
year's projects:
CAESAR:
Competition for Authenticated Encryption: Security,
Applicability, and Robustness
CAESAR: Round 2 Candidates
GMU Hardware API for Authenticated
Ciphers
Toward
a Universal HighSpeed Interface for Authenticated
Ciphers, GMU presentation at CryptArchi 2015,
Leuven, Belgium, June 28July 1, 2015
GMU
Supporting Materials for HighSpeed Implementation
of CAESAR Candidates
ATHENa Database of Results
ATHENa Website
DIAC  Directions in Authenticated
Ciphers, Singapore 2015
DIAC  Directions in Authenticated
Ciphers, Santa Barbara 2014
DIAC  Directions in Authenticated
Ciphers, Chicago 2013
DIAC  Directions in Authenticated
Ciphers, Stockholm 2012
NIST Cryptographic Toolkit
Advanced Encryption Standard  AES
eSTREAM: the
ECRYPT Stream Cipher Project
K. Gaj and P. Chodowiec, "FPGA
and ASIC Implementations of AES," Chapter 10 in
C.K. Koc (Ed.), Cryptographic Engineering, pp.
235320, Springer, Dec. 2008.
Examples of block diagrams for
cryptographic algorithms:
AES:
Interface with the Division into the
Datapath and Controller: AES_Enc,
AES_EncDec,
AES_Enc_KOF*
* KOF represents a version with the
round keys calculated on the fly
Keccak F Permutation:
Interface with the Division into the
Datapath and Controller: Keccak_F
Homework
Homework
5  due on
Saturday, Nov.
21, 2015,
11:59pm
Homework 4 (revised on Sat. Nov. 7) 
due on Monday,
Nov. 9, 2015,
11:59pm
Homework
3  due on Sunday, Oct. 25,
2015, 11:59pm, extended till
Thursday, Oct. 29, 6:00pm
Homework 2
 due on Thursday, Oct. 8,
2015, 7:20pm (in class)
Homework 1  due
on Saturday, Sep. 19, 2015, 11:59pm
Homework assignments will be posted
gradually here, at least 5 days before a given
assignment's due date.
Viewgraphs
Followup
Courses [ppt,
pdf]
Lecture 14
 ATHENa  Automated Tool for Hardware
EvaluatioN [ppt,
pdf]
ASM Chart
Example: AESCOPA by Farnoud Farahmand [pdf]
GMU
Hardware API for Authenticated Ciphers [pdf]
Verification
and Result Generation [ppt,
pdf]
Project
Deliverables [pdf]
Rules for
Reduced Complexity Block Diagrams,
developed by William
Diehl [pdf]
Lecture 13
 Controllers for Keccak_F and AES.
Advanced Coding Style for Datapaths. [ppt,
pdf]
Lecture 12  Design of Controllers using
Algorithmic State Machine (ASM) Charts. [ppt,
pdf]
Lecture 11
 Finite State Machines Refresher. [ppt,
pdf]
Lecture 10  FPGA Design
Flow. [ppt,
pdf]
Lecture
9  Behavioral Modeling of
SequentialCircuit Building Blocks. Mixing
Design Styles. Modeling of Circuits with a
Regular Structure. [ppt,
pdf]
Lecture 8 
Data Flow Description of
CombinationalCircuit Building Blocks. [ppt,
pdf]
Lecture 7  Data Flow Modeling in VHDL. [ppt,
pdf]
Lecture 6 
Advanced Testbenches. [ppt,
pdf]
Lecture 5B 
Block Diagrams. Hash Example. [ppt,
pdf]
Specifications of Class
Exercises: HASH
Lecture 5 
Block Diagrams. Modes of Operation of
Block Ciphers. [ppt,
pdf]
Lecture 4 
VHDL Basics. Simple Testbenches. [ppt,
pdf]
Lecture 3 
RTL Design Methodology. Transition from
Pseudocode & Interface to a Corresponding
Block Diagram. [ppt,
pdf]
Specifications of Class
Exercises: STATISTICS,
CIPHER
Lecture 2B 
Digital Logic Refresher. Part B – Sequential
Logic Building Blocks. [ppt,
pdf]
Lecture 2A  Digital Logic
Refresher. Part A – Combinational Logic Building
Blocks. [ppt,
pdf]
Lecture 1  Project Background [ppt,
pdf]
(revised on Sep. 10, 2015,
7:00pm)
Lecture 0  Organization and Introduction [ppt,
pdf]
Viewgraphs will be posted gradually
here.
Reference Material
VHDL
VHDL
Instructions: Templates & Examples
Frequently Asked Questions about
VHDL from comp.lang.vhdl
OpenCores
HDL
Modeling Guidelines
The Low
Carb VHDL Tutorial  by Bryan Mealy
vhdl.org
 HDL Resources of EDA Industry Working Groups
C
Tutorial on
Recommended Integrated Development Environment for
Running C Codes and Generating Test Vectors, available
on the page Tutorials
and Lab Manuals
Block Diagram
Editors
Please see a list of recommended
editors available on the page: Tools
Taught in ECE Classes, and additional
materials available on
the page: Tutorials
and Lab Manuals.
FPGA Tools
Please see Tutorials available on the
page: Tutorials
and Lab Manuals.
Use "545" or "ECE 545" as a filter.
Past Course Web
Pages
ECE 545:
Fall
2012 Fall
2013 Fall
2014
ECE 448:
Spring
2013 Spring 2014 Spring 2015
Practice
and
Past Exams
2014:
2013:
2012:
2011:
Solutions
to the Midterm Exam 2011: [PDF,
PPT]
Solutions to the Final Exam 2011
(selected deliverables in PDF):
2010:
2009:
2006:
2005:
2004:
