Time and location:

Monday,
7:2010:00 PM, Exploratory Hall, room L111

Instructor:


Email:

kgaj@gmu.edu

Office hours:

Monday
6:007:00 PM, Tuesday 7:308:30 PM, Friday 6:007:00 PM, and by
appointment
The
Engineering Building, room 3225



TA:


Office hours:

Monday,
6:007:00 PM, Thursday 7:309:30 PM


The
Engineering Building, Monday: room 3204, Thursday, room 3208

Email:

vdang6@gmu.edu

Please submit all your homework and project reports using
Blackboard
by going to http://mymasonportal.gmu.edu
Please use Piazza instead of email
for asking questions related to this class
Course Description
Introduces
the design of complex digital systems using hardware description
languages. Teaches
design methodologies which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code for digital circuit
design using dataflow, structural, and behavioral coding styles.
Introduces VHDL simulation and verification, and FPGA synthesis,
placement, routing, timing analysis, and performance optimization.
Requires semesterlong project devoted to the design of a complex
digital system implemented on FPGAs.
Prerequisites: Graduate
Standing. No official course prerequisite is required, but an
undergraduate background in digital logic design is strongly
recommended.
Required Textbooks
Pong P. Chu, RTL Hardware Design Using VHDL: Coding for
Efficiency, Portability, and Scalability, WileyIEEE Press,
2006.
Supplementary Textbooks
Ricardo
Jasinski, Effective
Coding with VHDL: Principles and Best Practice, 1st Edition, The
MIT Press, 2016.
Hubert
Kaeslin, Digital
Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication,
Cambridge University Press; 1st Edition, 2008.
Stephen Brown and Zvonko
Vranesic,
Fundamentals of Digital Logic with VHDL Design, 3rd Edition,
McGrawHill, 2008.
Volnei A. Pedroni,
Circuit
Design and Simulation with VHDL, 2nd Edition, The MIT Press,
2010.
Peter J. Ashenden,
The
Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann
Publishers, 2008.
Software Packages Used in This Class

Xilinx Vivado Design Suite
 ModelSim Intel FPGA
Full
versions of these packages will be available in the Computer
Engineering Labs, The Engineering Building, rooms 3208 and 3204.
FREE versions can be installed on your laptops and home
workstations.
Please see the installation instractions
available on the page: Tutorials and Lab
Manuals, under FPGA Tools.
Course Outline (subject to
possible modifications):
 Organization of the Course. Introduction
to FPGA Technology. Project. 08/27/2018
 Digital
Logic Refresher  Combinational Logic. 09/10/2018
 Digital
Logic Refresher  Sequential Logic. 09/17/2018
 RTL
Design Methodology  Part 1. 09/24/2018
 RTL
Design Methodology  Part 2.
10/01/2018
 VHDL
Fundamentals. 10/09/2018
 Testbenches.
Dataflow Modeling in VHDL. 10/15/2018
 Dataflow
Description of CombinationalCircuit Building Blocks in VHDL.
Behavioral Modeling of SequentialCircuit Building Blocks. Mixing
Design Styles. 10/22/2018
 Modeling of
Circuits with Regular Structure. VHDL2008. Poor Design Practices.
Measures of the
Circuit Performance. 10/29/2018
 Midterm Exam. 11/05/2018
 Finite State
Machines. Designing Controllers using Algorithmic State Machine (ASM)
charts. 11/12/2018
 Design of
Controllers using ASM Charts. 11/19/2018
 Modeling of
Memories in FPGAs. Using FPGA Embedded Resources. Project
Recommendations & Deliverables. 11/26/2018
 Timing
Analysis. Modern FPGAs. 12/03/2018
 Final Exam 12/17/2018
Project
This year's project will
involve implementing
Each group of students will design, implement, and optimize one
algorithm assigned to them by the instructor or proposed by themselves.
This project will support standardization organizations, such as NIST,
in selection of new cryptographic standards.
Homework
Homework 5, due Saturday, October 27, 11:59pm
+ Designs Under Test: debouncer.vhd and ALU.vhd
Homework 4,
due Saturday, October 13, 11:59pm
Homework 3,
due Saturday, October 6, 12:00 noon
Homework 2,
due Monday, September 24, 7:20pm
Homework 1,
due Monday, September 17, 7:20pm
Homework assignments will be posted
gradually here, at least 5 days before a given assignment is due.
Viewgraphs
Lecture 4  Testbenches. [pdf1,
pdf6]
Lecture 3  VHDL Fundamentals. [pdf1, pdf6]
Lecture 2  RTL Design Methodology. [pdf1,
pdf6]
(revised on 10/02/2018, added slides 3253)
STATISTICS
example  specification
CIPHER example 
specification
SORTING example

specification
Lecture 1B  Digital Logic Refresher.
Part A  Combinational Logic Building Blocks (Cont.). Part B 
Sequential Logic Building Blocks. [pdf1,
pdf6]
(updated 09/27/2018, added slides 6365)
Lecture 1A  Digital Logic Refresher.
Part A  Combinational Logic Building Blocks. [pdf1,
pdf6]
Lecture 0  Organization and
Introduction [pdf1, pdf6]
Viewgraphs will be posted gradually here.
Reference Material
VHDL
VHDL Instructions: Templates
& Examples
OpenCores
HDL Modeling Guidelines
The Low Carb VHDL Tutorial
 by Bryan Mealy
C
Block Diagram Editors
Please see a list of recommended editors
available on the page: Tools Taught in
ECE Classes, and additional materials available on the page: Tutorials and Lab
Manuals.
Past Course Web Pages
ECE
545: Fall 2017
Fall 2015
Fall 2014
Fall 2013
ECE 448: Spring
2018 Spring 2016
Spring 2015
Spring 2014
Practice
and Past Exams
2017:
2015:
2014:
2013:
2012:
2011:
Solutions to the Midterm Exam 2011: [PDF, PPT]
Solutions to the Final Exam 2011 (selected deliverables
in PDF):
2010:
2009:
2006:
2005:
2004:
