Time and location:
7:20-10:00 PM, Exploratory Hall, room L111
6:00-7:00 PM, Tuesday 7:30-8:30 PM, Friday 6:00-7:00 PM, and by
Engineering Building, room 3225
6:00-7:00 PM, Thursday 7:30-9:30 PM
Engineering Building, Monday: room 3204, Thursday, room 3208
Please submit all your homework and project reports using
by going to http://mymasonportal.gmu.edu
Please use Piazza instead of e-mail
for asking questions related to this class
the design of complex digital systems using hardware description
design methodologies which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code for digital circuit
design using dataflow, structural, and behavioral coding styles.
Introduces VHDL simulation and verification, and FPGA synthesis,
placement, routing, timing analysis, and performance optimization.
Requires semester-long project devoted to the design of a complex
digital system implemented on FPGAs.
Standing. No official course prerequisite is required, but an
undergraduate background in digital logic design is strongly
Pong P. Chu, RTL Hardware Design Using VHDL: Coding for
Efficiency, Portability, and Scalability, Wiley-IEEE Press,
Coding with VHDL: Principles and Best Practice, 1st Edition, The
MIT Press, 2016.
Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication,
Cambridge University Press; 1st Edition, 2008.
Stephen Brown and Zvonko
Fundamentals of Digital Logic with VHDL Design, 3rd Edition,
Volnei A. Pedroni,
Design and Simulation with VHDL, 2nd Edition, The MIT Press,
Peter J. Ashenden,
Designer's Guide to VHDL, 3rd Edition, Morgan Kaufmann
Software Packages Used in This Class
Xilinx Vivado Design Suite
- ModelSim Intel FPGA
versions of these packages will be available in the Computer
Engineering Labs, The Engineering Building, rooms 3208 and 3204.
FREE versions can be installed on your laptops and home
Please see the installation instractions
available on the page: Tutorials and Lab
Manuals, under FPGA Tools.
Course Outline (subject to
- Organization of the Course. Introduction
to FPGA Technology. Project. 08/27/2018
Logic Refresher - Combinational Logic. 09/10/2018
Logic Refresher - Sequential Logic. 09/17/2018
Design Methodology - Part 1. 09/24/2018
Design Methodology - Part 2.
Modeling in VHDL. VHDL
Description of Basic Combinational Building
Description of Basic Sequential Building
Blocks. Poor Design Practices.
- Midterm Exam. 11/05/2018
- Modeling of
Circuits with Regular Structure. Finite
Machine Refresher. 11/12/2018
Controllers using Algorithmic State Machine (ASM)
of Solutions to the Midterm Exam. Project
Recommendations & Deliverables. 11/26/2018
- VHDL-2008. Timing
- Final Exam 12/16/2018
This year's project will
Each group of students will design, implement, and optimize one
algorithm assigned to them by the instructor or proposed by themselves.
This project will support standardization organizations, such as NIST,
in selection of new cryptographic standards.
Complexity Block Diagrams
due Sunday, November 18, 11:59pm
- revised on 11/17/2018, 11:00am
due Friday, November 2, 11:59pm
+ Designs Under Test: debouncer.vhd
due Saturday, October 13, 11:59pm
due Saturday, October 6, 12:00 noon
due Monday, September 24, 7:20pm
due Monday, September 17, 7:20pm
Homework assignments will be posted
gradually here, at least 5 days before a given assignment is due.
A follow-up course: ECE 645 Computer
Lecture 12 - Timing Analysis. [pdf-1,
Lecture 11 - VHDL-2008 [see slides on
Lecture 10 - Design of Controllers using
Algorithmic State Machine (ASM) Charts. [pdf-1, pdf-6]
Lecture 9 - Finite State Machine
Refresher. [pdf-1, pdf-6]
Lecture 8 - Modeling of Circuits with
Regular Structure. [pdf-1, pdf-6]
Lecture 7 - Poor Design Practices &
Their Remedies. [pdf-1, pdf-6]
Lecture 6 - VHDL Description of Basic
Combinational & Sequential Circuit Building Blocks. [pdf-1,
Lecture 5 - Dataflow Modeling in VHDL. [pdf-1,
Lecture 4 - Testbenches. [pdf-1,
Lecture 3 - VHDL Fundamentals. [pdf-1, pdf-6]
Lecture 2 - RTL Design Methodology. [pdf-1,
(revised on 10/02/2018, added slides 32-53)
example - specification
CIPHER example -
Lecture 1B - Digital Logic Refresher.
Part A - Combinational Logic Building Blocks (Cont.). Part B -
Sequential Logic Building Blocks. [pdf-1,
(updated 09/27/2018, added slides 63-65)
Lecture 1A - Digital Logic Refresher.
Part A - Combinational Logic Building Blocks. [pdf-1,
Lecture 0 - Organization and
Introduction [pdf-1, pdf-6]
Viewgraphs will be posted gradually here.
VHDL Instructions: Templates
HDL Modeling Guidelines
The Low Carb VHDL Tutorial
- by Bryan Mealy
Block Diagram Editors
Please see a list of recommended editors
available on the page: Tools Taught in
ECE Classes, and additional materials available on the page: Tutorials and Lab
Past Course Web Pages
545: Fall 2017
ECE 448: Spring
2018 Spring 2016
and Past Exams
Solutions to the Midterm Exam 2011: [PDF, PPT]
Solutions to the Final Exam 2011 (selected deliverables