Time and location:
7:20-10:00 PM, Music Theater Building (formerly Fine Arts Building), room 1002
6:00-7:00 PM, Wednesday 7:30-8:30 PM, Friday 6:00-7:00 PM, and by
Engineering Building, room 3225
Please submit all your homework and project reports using
by going to http://mymasonportal.gmu.edu
Please use Piazza instead of e-mail for asking questions related to this class
Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis, and performance optimization.
Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs.
Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly
Pong P. Chu, RTL Hardware Design Using VHDL: Coding for
Efficiency, Portability, and Scalability, Wiley-IEEE Press,
Coding with VHDL: Principles and Best Practice, 1st Edition, The
MIT Press, 2016.
Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer,
Parallel Programming for FPGAs: The HLS Book, 2018.
Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication,
Cambridge University Press; 1st Edition, 2008.
Stephen Brown and Zvonko
Fundamentals of Digital Logic with VHDL Design, 3rd Edition,
Software Packages Used in This Class
Xilinx Vivado Design Suite
- ModelSim Intel FPGA
versions of these packages will be available in the Computer
Engineering Labs, The Engineering Building, rooms 3208 and 3204.
FREE versions can be installed on your laptops and home
Course Outline (subject to
- Organization of the Course. Introduction to FPGA Technology. Project. 08/26/2019
- Digital Logic Refresher - Combinational Logic. 09/09/2019
- Digital Logic Refresher - Sequential Logic. 09/16/2019
- RTL Design Methodology - Part 1. 09/23/2019
- RTLDesign Methodology - Part 2. 09/30/2019
- VHDLFundamentals. 10/07/2019
- Testbenches. 10/15/2019
- Dataflow Modeling in VHDL. VHDL Description of Basic Combinational Building Blocks. 10/21/2019
- VHDL Description of Basic Sequential Building Blocks. Poor Design Practices. 10/28/2019
- Midterm Exam. 11/04/2019
- Modeling of Circuits with Regular Structure. Finite State Machine Refresher. 11/11/2019
- Designing Controllers using Algorithmic State Machine (ASM) charts - Part 1. 11/18/2019
- Designing Controllers using Algorithmic State Machine (ASM) charts - Part 2. Timing Analysis. Project Recommendations & Deliverables. 11/25/2019
- VHDL-2008. Chisel. High-Level Synthesis. Software/Hardware Codesign. 12/02/2019
- Final Exam 12/16/2019
This year's project will involve implementing
Each group of students will design, implement, and optimize one
algorithm assigned to them by the instructor or proposed by themselves.
This project will support standardization organizations, such as NIST,
in selection of new cryptographic standards.
Complexity Block Diagrams
Homework assignments will be posted
gradually here, at least 5 days before a given assignment is due.
Viewgraphs will be posted gradually here.
VHDL Instructions: Templates
HDL Modeling Guidelines
The Low Carb VHDL Tutorial
- by Bryan Mealy
Block Diagram Editors
Please see a list of recommended editors
available on the page: Tools Taught in
ECE Classes, and additional materials available on the page: Tutorials and Lab
Past Course Web Pages
Practice and Past Exams
Solutions to the Final Exam 2018:
Solutions to the Midterm Exam 2011: [PDF, PPT]
Solutions to the Final Exam 2011 (selected deliverables