Time and location:
7:20-10:00 PM, Music Theater Building (formerly Fine Arts Building), room 1002
6:00-7:00 PM, Wednesday 7:30-8:30 PM, Friday 6:00-7:00 PM, and by
Engineering Building, room 3225
Monday 3:30-6:10 PM, Friday 5:15-6:35 PM
Engineering Building, room 3204
Please submit all your homework and project reports using
by going to http://mymasonportal.gmu.edu
Please use Piazza instead of e-mail for asking questions related to this class
Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis, and performance optimization.
Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs.
Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly
Pong P. Chu, RTL Hardware Design Using VHDL: Coding for
Efficiency, Portability, and Scalability, Wiley-IEEE Press,
Coding with VHDL: Principles and Best Practice, 1st Edition, The
MIT Press, 2016.
Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer,
Parallel Programming for FPGAs: The HLS Book, 2018.
Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication,
Cambridge University Press; 1st Edition, 2008.
Stephen Brown and Zvonko
Fundamentals of Digital Logic with VHDL Design, 3rd Edition,
Software Packages Used in This Class
Xilinx Vivado Design Suite
- ModelSim Intel FPGA
versions of these packages will be available in the Computer
Engineering Labs, The Engineering Building, rooms 3208 and 3204.
FREE versions can be installed on your laptops and home
Please see the installation instractions
available on the page: Tutorials and Lab
Manuals, under FPGA Tools.
Course Outline (subject to possible modifications):
- Organization of the Course. Introduction to FPGA Technology. Project. 08/26/2019
- Digital Logic Refresher - Combinational Logic. 09/09/2019
- Digital Logic Refresher - Sequential Logic. 09/16/2019
- RTL Design Methodology - Part 1. 09/23/2019
- RTL Design Methodology - Part 2. 09/30/2019
- VHDL Fundamentals. 10/07/2019
- Benchmarking Framework. Testbenches - Part 1. 10/15/2019
- Testbenches - Part 2. Dataflow Modeling in VHDL. 10/21/2019
- VHDL Description of Basic Combinational and Sequential Circuit Building Blocks. Poor Design Practices. 10/28/2019
- Midterm Exam. 11/04/2019
- Modeling of Circuits with Regular Structure. 11/11/2019
- Finite State Machine Refresher. Algorithmic State Machine Charts. 11/18/2019
- Designing Controllers using Algorithmic State Machine (ASM) charts. Project Recommendations & Deliverables. 11/25/2019
- Designing Controllers - VHDL Coding Styles. Timing Analysis. VHDL-2008. 12/02/2019
- Final Exam 12/15/2019
This year's project will involve implementing
Each group of students will design, implement, and optimize one
algorithm assigned to them by the instructor or proposed by themselves.
This project will support standardization organizations, such as NIST,
in selection of new cryptographic standards.
GMU ATHENa: Lightweight Cryptography
Reduced Complexity Block Diagrams
Examples of 5-port Wrappers
Homework 5, due Sunday, December 8, 11:59pm
Homework 4, due Sunday, November 10, 11:59pm + Testbenches [testbench_examples.zip] + Designs Under Test [debouncer.vhd, ALU.vhd]
Homework 3, due Monday, September 30, 7:20pm
Homework 3 - Bonus, due Sunday, September 29, 11:59pm
Homework 2, due Monday, September 23, 7:20pm
Homework 1, due Monday, September 16, 7:20pm
Homework assignments will be posted gradually here, at least 5 days before a given assignment is due.
Lecture 14 - VHDL-2008 [see slides on Piazza]
Lecture 13 - Timing Analysis. [pdf-1, pdf-6]
Lecture 12 - Design of Controllers Using ASM Charts. [pdf-1, pdf-6]
Lecture 11 - Algorithmic State Machine Charts. [pdf-1, pdf-6]
Lecture 10 - Finite State Machine Refresher. [pdf-1, pdf-6]
Lecture 9 - RAM. [pdf-1, pdf-6]
Lecture 8 - Modeling of Circuits with Regular Structure. [pdf-1, pdf-6]
Lecture 7 - Poor Design Practices &Their Remedies. [pdf-1, pdf-6]
Lecture 6 - VHDL Description of Basic Combinational & Sequential Circuit Building Blocks. [pdf-1, pdf-6]
Lecture 5 - Dataflow Modeling in VHDL. [pdf-1, pdf-6]
Lecture 4 - Testbenches. [pdf-1, pdf-6]
Lecture 3 - VHDL Fundamentals. [pdf-1, pdf-6]
Lecture 2B - RTL Design Methodology. [pdf-1, pdf-6]
Lecture 2A - RTL Design Methodology. [pdf-1, pdf-6]
STATISTICS example - specification
CIPHER example - specification
Lecture 1B - Digital Logic Refresher. Part A - Combinational Logic Building Blocks (Cont.) Part B - Sequential Logic Building Blocks. [pdf-1,
Lecture 1A - Digital Logic Refresher.
Part A - Combinational Logic Building Blocks. [pdf-1,
Lecture 0 - Organization and
Introduction [pdf-1, pdf-6]
Viewgraphs will be posted gradually here.
VHDL Instructions: Templates
HDL Modeling Guidelines
The Low Carb VHDL Tutorial
- by Bryan Mealy
Block Diagram Editors
Please see a list of recommended editors
available on the page: Tools Taught in
ECE Classes, and additional materials available on the page: Tutorials and Lab
Past Course Web Pages
Practice and Past Exams
Solutions to the Final Exam 2018:
Solutions to the Midterm Exam 2011: [PDF, PPT]
Solutions to the Final Exam 2011 (selected deliverables