ECE 545
Digital System Design with VHDL

Fall 2019

Time and location:

Monday, 7:20-10:00 PM, Music Theater Building (formerly Fine Arts Building), room 1002


Kris Gaj


Office hours:

Monday 6:00-7:00 PM, Wednesday 7:30-8:30 PM, Friday 6:00-7:00 PM, and by appointment

The Engineering Building, room 3225


Ahmed Ferozpuri

Office hours:

Monday 3:30-6:10 PM, Friday 5:15-6:35 PM

The Engineering Building, room 3204


Please submit all your homework and project reports using Blackboard by going to

Please use Piazza instead of e-mail for asking questions related to this class 

Course Description

Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis, and performance optimization. Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs. 

Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly recommended.

Required Textbooks

Pong P. ChuRTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006.

Supplementary Textbooks

Ricardo Jasinski, Effective Coding with VHDL: Principles and Best Practice, 1st Edition, The MIT Press, 2016.

Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer, Parallel Programming for FPGAs: The HLS Book, 2018.

Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Edition, McGraw-Hill, 2008.

Software Packages Used in This Class

  • Xilinx Vivado Design Suite

  • ModelSim Intel FPGA

Full versions of these packages will be available in the Computer Engineering Labs, The Engineering Building, rooms 3208 and 3204.
FREE versions can be installed on your laptops and home workstations.

Please see the installation instractions available on the page: Tutorials and Lab Manuals, under FPGA Tools.

Course Outline (subject to possible modifications):

  1. Organization of the Course. Introduction to FPGA Technology. Project.  08/26/2019
  2. Digital Logic Refresher - Combinational Logic.   09/09/2019
  3. Digital Logic Refresher - Sequential Logic.   09/16/2019
  4. RTL Design Methodology - Part 1.   09/23/2019
  5. RTL Design Methodology - Part 2.   09/30/2019
  6. VHDL Fundamentals.   10/07/2019
  7. Benchmarking Framework. Testbenches - Part 1.   10/15/2019
  8. Testbenches - Part 2. Dataflow Modeling in VHDL.   10/21/2019
  9. VHDL Description of Basic Combinational and Sequential Circuit Building Blocks. Poor Design Practices.   10/28/2019
  10. Midterm Exam.   11/04/2019
  11. Modeling of Circuits with Regular Structure.   11/11/2019
  12. Finite State Machine Refresher. Algorithmic State Machine Charts.   11/18/2019
  13. Designing Controllers using Algorithmic State Machine (ASM) charts. Project Recommendations & Deliverables.   11/25/2019
  14. Designing Controllers - VHDL Coding Styles. Timing Analysis. VHDL-2008.   12/02/2019
  15. Final Exam   12/15/2019


This year's project will involve implementing Each group of students will design, implement, and optimize one algorithm assigned to them by the instructor or proposed by themselves. This project will support standardization organizations, such as NIST, in selection of new cryptographic standards.

GMU ATHENa: Lightweight Cryptography

Project Recommendations

Project Deliverables

Reduced Complexity Block Diagrams

Examples of 5-port Wrappers


Homework 5, due Sunday, December 8, 11:59pm

Homework 4, due Sunday, November 10, 11:59pm + Testbenches [] + Designs Under Test [debouncer.vhd, ALU.vhd]

Homework 3, due Monday, September 30, 7:20pm

Homework 3 - Bonus, due Sunday, September 29, 11:59pm

Homework 2, due Monday, September 23, 7:20pm

Homework 1, due Monday, September 16, 7:20pm

Homework assignments will be posted gradually here, at least 5 days before a given assignment is due.


Lecture 14 - VHDL-2008 [see slides on Piazza]

Lecture 13 - Timing Analysis. [pdf-1, pdf-6]

Lecture 12 - Design of Controllers Using ASM Charts. [pdf-1, pdf-6]

Lecture 11 - Algorithmic State Machine Charts. [pdf-1, pdf-6]

Lecture 10 - Finite State Machine Refresher. [pdf-1, pdf-6]

Lecture 9 - RAM. [pdf-1, pdf-6]

Lecture 8 - Modeling of Circuits with Regular Structure. [pdf-1, pdf-6]

Lecture 7 - Poor Design Practices &Their Remedies. [pdf-1, pdf-6]

Lecture 6 - VHDL Description of Basic Combinational & Sequential Circuit Building Blocks. [pdf-1, pdf-6]

Lecture 5 - Dataflow Modeling in VHDL. [pdf-1, pdf-6]

Lecture 4 - Testbenches. [pdf-1, pdf-6]

Lecture 3 - VHDL Fundamentals. [pdf-1, pdf-6]

Lecture 2B - RTL Design Methodology. [pdf-1, pdf-6]

Lecture 2A - RTL Design Methodology. [pdf-1, pdf-6]

STATISTICS example - specification

CIPHER example - specification

Lecture 1B - Digital Logic Refresher. Part A - Combinational Logic Building Blocks (Cont.) Part B - Sequential Logic Building Blocks. [pdf-1, pdf-6]

Lecture 1A - Digital Logic Refresher. Part A - Combinational Logic Building Blocks. [pdf-1, pdf-6]

Lecture 0 - Organization and Introduction [pdf-1, pdf-6]

Viewgraphs will be posted gradually here.


Reference Material


VHDL Instructions: Templates & Examples

OpenCores HDL Modeling Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy



Top 10 C Language resources that will turn you into a better programmer

C Tutorial

Block Diagram Editors

Please see a list of recommended editors available on the page: Tools Taught in ECE Classes, and additional materials available on the page: Tutorials and Lab Manuals.

Past Course Web Pages

ECE 545:   Fall 2018  Fall 2017  Fall 2015  Fall 2014  Fall 2013 

ECE 448:   Spring 2019  Spring 2018  Spring 2016  Spring 2015  Spring 2014 


Practice and Past Exams


Final Exam 2018

Solutions to the Final Exam 2018:

Midterm Exam 2018

Solutions to the Midterm Exam 2018


Final Exam 2017

Solutions to the Final Exam 2017

Midterm Exam 2017

Solutions to the Midterm Exam 2017


Final Exam 2015

Midterm Exam 2015


Final Exam 2014 + Answer Sheet for Problem 3 + Answer Sheet for Problem 4

Solutions to the Final Exam 2014

Midterm Exam 2014 + Fill-in-the-blanks Problem 2


Final Exam 2013

Best Student Solution to Final Exam 2013

Solutions to the Problems 2A and 2B from the Final Exam 2013

Midterm Exam 2013

Solutions to the Midterm Exam 2013


Midterm Exam 2012

Solutions to the Midterm Exam 2012:  Task 1, Task 1 (alternative designs for key storage), Task 2, Task 3, Task 5

Source codes for Task 4:  XTEA_pkg.vhd  ROUND.vhd

Final Exam 2012

Best Student Solution to the Final Exam 2012


Midterm Exam 2011

Solutions to the Midterm Exam 2011:  [PDF, PPT]

Source codes for Task 3:  reg.vhd, ROM_16x4.vhd, main_iterative_loop.vhd

Source Codes for Task 5:  exam_top_tb.vhd

Final Exam 2011

Solutions to the Final Exam 2011:  all deliverables (zip)

Solutions to the Final Exam 2011 (selected deliverables in PDF): 

  block diagram, interface, ASM chart, short report


Midterm Exam 2010

Final Exam 2010

Best Student Solution to Final Exam 2010


Midterm Exam 2009

Solutions to the Midterm Exam 2009: Task 1  Task 2  Task 3  Task 4

Midterm Exam 2009: Recommended Reading and Practice Problems

Final Exam 2009


Midterm Exam 1 from Fall 2006

Midterm Exam 2 from Fall 2006


Midterm Exam 1 from Fall 2005

Midterm Exam 2 from Fall 2005


Midterm Exam 1 from Fall 2004

Midterm Exam 2 from Fall 2004