ECE 699

Software/Hardware Codesign
Spring 2016

Time and location: Thursday, 7:20-10:00 PM, Exploratory Hall, room L111
Instructor: Kris Gaj
Email: kgaj (at)
Office hours: Monday 3:00-4:00 PM, Wednesday 3:00-4:00 PM, Thursday 6:00-7:00 PM, and by appointment, all in ENGR 3225
Co-Instructor: Farnoud Farahmand
Email: ffarahma (at)
Office hours: Wednesday, 12:00-2:00pm in ENGR 3208, 6:00-8:00pm in ENGR 3204, and by appointment
Prerequisites: ECE 511 and ECE 545, or equivalent; knowledge of C and VHDL at the intermediate level or beyond
Syllabus: TBD

Required Textbooks:

L.H. Crockett, R.A. Elliot, M.A. Enderwitz, R.W. Stewart, and D. Northcote, The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC, University of Strathlyde, Glasgow, UK, PDF copy available for free at

L.H. Crockett, R.A. Elliot, M.A. Enderwitz, and R.W. Stewart, The Zynq Book Tutorials, University of Strathlyde, Glasgow, UK, available for free at

Supplementary Textbooks:

P.R. Schaumont, A Practical Introduction to Hardware/Software Codesign, 2nd Ed, Springer, 2012, available for free for GMU students at Springer Link,

P.P. Chu, Embedded SoPC Design with Nios II Processor and VHDL Examples, 1st Ed., Wiley, 2011.


Development Board:

Course Outline (subject to possible modifications):

  1.    Objectives, Scope, and Organization.   01/21/2016
Introduction to ZYNQ. ZYNQ Design Flow.  01/29/2016
  3.    General Purpose Input Output, GPIO.
Class Exercise 1: First Design on ZYNQ.  02/04/2016
  4.    Interrupts. AXI GPIO and AXI Timer. Class Exercise 2: Next Steps in Zynq SoC Design.  02/11/2016
  5.    AXI Interfacing. Using DMA & AXI4-Stream.  02/18/2016
  6.    Custom IP Generation. Efficient Communication Between Custom IPs and PS. Class Exercise 3: Using DMA and AXI4-Stream for communication with a hardware accelerator.   02/25/2016
  7.    Efficient Communication Between Hardware Accelerators and PS.  03/03/2016
  8.    Programmable Logic Memories.  Memory Interfacing.  03/17/2016
  9.    Midterm Exam.  03/24/2016
Profiling Tools. Logic Analyzer. Class Exercise 4: Profiling and Using Integrated Logic Analyzer.  03/31/2016
High-Level Synthesis – Part 1.  Class Exercise 5: Designing with Vivado High Level Synthesis.  04/07/2016
High-Level Synthesis – Part 2.  Vivado HLS Introduction. 04/14/2016
13.    High-Level Synthesis – Part 3.  Performance and Resource Optimization.  Class Exercise 6: Optimization of HLS Codes.   04/21/2016
14.    Configuration and Bootloading. 04/28/2016
15.    Final Exam.  05/05/2016, 6:45-8:45pm

16.    Project Presentations.  05/09/2016

Lecture Slides

Bonus Lecture: Linux on Zynq (not covered at the exam)

Lectures 16 - Configuration and Bootloading [available on Piazza, under Resources]

Lectures 14-15 - Vivado HLS - Example: 16x16 Matrix Multiply [available on Piazza, under Resources]

       whiteboard diagram

Lecture 15 - Vivado HLS - Improving Resources [available on Piazza, under Resources]

Lecture 14 - Vivado HLS - Improving Performance [available on Piazza, under Resources]

Lecture 13b - Using Vivado HLS [available on Piazza, under Resources]

Lecture 13a - Introduction to High-Level Synthesis with Vivado HLS [available on Piazza, under Resources]

Lecture 12 - Introduction to High-Level Synthesis [ppt, pdf]

Lecture 11 - Integrated Logic Analyzer & Profiling [ppt, pdf]

Lecture 10 - Memory Interfacing [available on Piazza, under Resources]

Lecture 9 - Programmable Logic Memories. [ppt, pdf]

Lecture 8 - Efficient Communication Between Hardware Accelerators and PS. [ppt, pdf]

Lecture 7 - Custom IP Generation. Efficient Communication Between Custom IPs and PS. [ppt, pdf]

Lecture 6 - AXI Interfacing. Using DMA & AXI4-Stream. [ppt, pdf]

Lecture 5 - Interrupts. AXI GPIO and AXI Timer. [ppt, pdf]

Lecture 4 - General Purpose Input Output, GPIO [ppt, pdf]

Lecture 3 - ZYNQ Design Flow [ppt, pdf]

Lecture 2 - Introduction to ZYNQ [ppt, pdf]

Lecture 1 - Objectives, Scope, and Organization [ppt, pdf]

Posted gradually before a given lecture.

Class Exercise Tutorials

Working with MIO LEDs and Pushbuttons    led_btns_ps.c

Xilinx Sources and Documentation   

Memory Allocation in Xilinx SDK Environment


Homework Assignments

Homework Assignment 1 - Using AXI GPIO, Interrupts, and AXI Timer - due Wednesday,  02/24, 6:00 PM

Homework Assignment 2/3 - Custom IP Creation, AXI Stream Transaction and Testbench in Vivado Environment - due Thursday, 03/24, 5:00 PM

All exercises and assignments can be done individually or in a group of two students (group homework assignments will involve a larger number of tasks and/or more time-consuming tasks).

Class exercises that are not completed during the class time are expected to be finished at home.

Homework assignments are expected to be completed outside of the lecture time. Homework deliverables must be submitted on Blackboard by the specified deadline, and the required operation of the ZYNQ-based system and/or tools demonstrated to Farnoud during his office hours on Wednesday, 6:00-8:00pm (or after the class the latest). If any of these two conditions is not met, the assignment may be considered one-week late, and penalized with 33% of points. If you expect to be on travel or you are sick in a given week, please do your best to inform the instructor and the TA as soon as you realize that you are likely to miss the class. No submissions will be accepted more than one week after its respective deadline. Honor code will be strictly enforced.

Grading Scheme

Class Exercises 5%
Homework Assignments 10%
Project 35%
Midterms Exam 20%
Final Exam
Class Activity up to 5%
of bonus points


Tentative Schedule of Project Presentations

The project in this course can be used to

Common Requirements

Common Tasks

Possible Extensions

Resources for Project Topics Recommended by the Instructor

Post-Quantum Cryptosystems

Authenticated Ciphers

Hash Functions

Computer Vision and Machine Learning Algorithms

Other Potential Project Areas

Useful Resources


M.S. Sadri, ZYNQ Training

Xilinx, ZYNQ Video Tutorials

Xilinx, Vivado Video Tutorials

Xilinx, Vivado Design Suite Tutorial: Programming and Debugging

Xilinx, Vivado Design Suite Tutorial: High-Level Synthesis

S. Neuendorffer and F. Martinez-Vallina, Building Zynq Accelerators with Vivado High Level Synthesis, FPGA 2013 Tutorial

FPGA Tool Tutorials available on the page: Tutorials and Lab Manuals

Embedded Linux Tutorial - ZYBO

Reference Manuals and User Guides

Xilinx, Zynq-7000 All Programmable SoC Technical Reference Manual

Digilent, ZYBO Reference Manual

Xilinx, Introduction to FPGA Design with Vivado High-Level Synthesis

Xilinx, Vivado Design Suite User Guide: High-Level Synthesis


Xcell Journal

Electronic Engineering Journal: FPGA and Programmable Logic Design

C Resources

Top 10 C Language resources that will turn you into a better programmer

C Programming Tutorial

VHDL Resources

VHDL Instructions: Templates & Examples

Frequently Asked Questions about VHDL from comp.lang.vhdl

OpenCores Coding Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy - HDL Resources of EDA Industry Working Groups

Related course web pages

ECE 699: Spring 2015

ECE 511: Fall 2014

ECE 545: Fall 2015

ECE 645: Spring 2014

ECE 448: Spring 2015


Spring 2016 Midterm Exam, Part 1: Concepts:  text  solutions

Spring 2016 Midterm Exam, Part 2: Practice:  text

Spring 2015 Final Exam, Part 1: Concepts:  text

Spring 2015 Midterm Exam, Part 1: Concepts:  text  solutions

Spring 2015 Midterm Exam, Part 2: Practice:  text  codes