|Time and location:||Thursday, 7:20-10:00 PM, Exploratory Hall, room L111|
|Email:||kgaj (at) gmu.edu|
|Office hours:||Monday 3:00-4:00 PM, Wednesday 3:00-4:00 PM, Thursday 6:00-7:00 PM, and by appointment, all in ENGR 3225|
|Co-Instructor:|| Farnoud Farahmand
|Email:||ffarahma (at) masonlive.gmu.edu|
|Office hours:||Wednesday, 12:00-2:00pm in ENGR 3208, 6:00-8:00pm in ENGR 3204, and by appointment|
511 and ECE
545, or equivalent; knowledge of C and VHDL at the intermediate
level or beyond
L.H. Crockett, R.A. Elliot, M.A. Enderwitz, R.W. Stewart, and D. Northcote, The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC, University of Strathlyde, Glasgow, UK, PDF copy available for free at http://www.zynqbook.com.
L.H. Crockett, R.A. Elliot, M.A. Enderwitz, and R.W. Stewart, The Zynq Book Tutorials, University of Strathlyde, Glasgow, UK, available for free at http://www.zynqbook.com/download-tuts.html.
P.R. Schaumont, A Practical Introduction to Hardware/Software Codesign, 2nd Ed, Springer, 2012, available for free for GMU students at Springer Link, http://link.springer.com.mutex.gmu.edu.
P.P. Chu, Embedded SoPC Design with Nios II Processor and VHDL Examples, 1st Ed., Wiley, 2011.
Inc. ZYBO Zynq™-7000 Development Board, distributed for free
at the beginning of the semester, and collected at the end of the
Course Outline (subject to possible modifications):
Bonus Lecture: Linux on Zynq (not
covered at the exam)
Lectures 16 - Configuration and Bootloading [available on Piazza, under Resources]
Lectures 14-15 - Vivado HLS - Example: 16x16 Matrix Multiply [available on Piazza, under Resources]
Lecture 15 - Vivado HLS - Improving Resources [available on Piazza, under Resources]
Lecture 14 - Vivado HLS - Improving Performance [available on Piazza, under Resources]
Lecture 13b - Using Vivado HLS [available on Piazza, under Resources]
Lecture 13a - Introduction to High-Level Synthesis with Vivado HLS [available on Piazza, under Resources]
Lecture 12 - Introduction to High-Level Synthesis [ppt, pdf]
Lecture 11 - Integrated
Logic Analyzer & Profiling [ppt, pdf]
Lecture 10 - Memory
Interfacing [available on Piazza, under Resources]
Lecture 9 - Programmable Logic Memories. [ppt, pdf]
Lecture 8 - Efficient Communication Between Hardware Accelerators and PS. [ppt, pdf]
Lecture 7 - Custom IP Generation. Efficient Communication Between
Custom IPs and PS. [ppt, pdf]
Lecture 6 - AXI Interfacing. Using DMA & AXI4-Stream. [ppt, pdf]
Lecture 5 - Interrupts. AXI GPIO and AXI Timer. [ppt, pdf]
Lecture 4 - General Purpose Input Output, GPIO [ppt, pdf]
Lecture 3 - ZYNQ Design Flow [ppt, pdf]
Lecture 2 - Introduction to ZYNQ [ppt, pdf]
Lecture 1 - Objectives, Scope, and Organization [ppt, pdf]
gradually before a given lecture.
Working with MIO LEDs and Pushbuttons led_btns_ps.c
Allocation in Xilinx SDK Environment
Homework Assignment 1 - Using AXI GPIO, Interrupts, and AXI Timer - due Wednesday, 02/24, 6:00 PM
Homework Assignment 2/3 - Custom IP
Creation, AXI Stream Transaction and Testbench in Vivado Environment
- due Thursday, 03/24, 5:00 PM
All exercises and assignments can be done
individually or in a group of two students (group homework assignments
will involve a larger number of tasks and/or more time-consuming tasks).
Class exercises that are not completed during the class time are expected to be finished at home.
Homework assignments are expected to be completed outside of the lecture time. Homework deliverables must be submitted on Blackboard by the specified deadline, and the required operation of the ZYNQ-based system and/or tools demonstrated to Farnoud during his office hours on Wednesday, 6:00-8:00pm (or after the class the latest). If any of these two conditions is not met, the assignment may be considered one-week late, and penalized with 33% of points. If you expect to be on travel or you are sick in a given week, please do your best to inform the instructor and the TA as soon as you realize that you are likely to miss the class. No submissions will be accepted more than one week after its respective deadline. Honor code will be strictly enforced.
|Class Activity||up to 5%
of bonus points
The project in this course can be used to
Resources for Project Topics Recommended by the Instructor
Computer Vision and Machine Learning Algorithms
Other Potential Project Areas